公开(公告)号：US20120199972A1

公开(公告)日：2012-08-09

申请号：US13446863

申请日：2012-04-13

Applicant: Reza A. Pagaila ,  Byung Tai Do ,  Shuangwu Huang ,  Rajendra D. Pendse

Inventor： Reza A. Pagaila ,  Byung Tai Do ,  Shuangwu Huang ,  Rajendra D. Pendse

IPC: H01L23/498 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L23/3128 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/48 ,  H01L24/73 ,  H01L24/86 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/20 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is made by forming a conductive layer over a temporary carrier. The conductive layer includes a wettable pad. A stud bump is formed over the wettable pad. The stud bump can be a stud bump or stacked bumps. A semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the stud bump. A first interconnect structure is formed over a first surface of the encapsulant. The first interconnect structure includes a first IPD and is electrically connected to the stud bump. The carrier is removed. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The second interconnect structure includes a second IPD. The first or second IPD includes a capacitor, resistor, or inductor. The semiconductor devices are stackable and electrically connected through the stud bump.

Abstract translation: 通过在临时载体上形成导电层制成半导体器件。 导电层包括可湿性垫。 在可湿性垫上形成柱状凸块。 螺栓凸块可以是螺柱凸块或堆叠的凸块。 半导体管芯安装在载体上。 密封剂沉积在半导体管芯上并且在螺柱凸块周围。 在密封剂的第一表面上形成第一互连结构。 第一互连结构包括第一IPD并且电连接到螺柱凸块。 载体被移除。 在与第一互连结构相对的密封剂的第二表面上形成第二互连结构。 第二互连结构包括第二IPD。 第一或第二IPD包括电容器，电阻器或电感器。 半导体器件可堆叠并通过柱形凸起电连接。

公开(公告)号：US08227910B2

公开(公告)日：2012-07-24

申请号：US13212986

申请日：2011-08-18

Applicant: Reza A. Pagaila ,  Byung Tai Do ,  Zigmund R. Camacho

Inventor： Reza A. Pagaila ,  Byung Tai Do ,  Zigmund R. Camacho

IPC: H01L23/04

CPC classification number: H01L23/3121 ,  H01L21/568 ,  H01L23/3677 ,  H01L23/4334 ,  H01L24/19 ,  H01L24/48 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82001 ,  H01L2224/9222 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a semiconductor die having contact pads. An encapsulant is disposed around the semiconductor die, and conductive vias are disposed in the encapsulant. Electrically conductive traces are disposed between the contact pads and conductive vias, a thermally conductive channel is disposed in the encapsulant separate from the conductive vias, and a thermally conductive layer is disposed over an area of heat generation of the semiconductor die. A thermally conductive trace is disposed between the thermally conductive layer and thermally conductive channel. The thermally conductive layer, thermally conductive trace, and thermally conductive channel are electrically isolated from the contact pads of the semiconductor die and the electrically conductive traces. The semiconductor package further comprises broad thermal traces disposed over the encapsulant, and a thermally conductive material interconnecting the broad thermal traces and the thermally conductive layer.

Abstract translation: 半导体封装包括具有接触焊盘的半导体管芯。 密封剂设置在半导体管芯周围，并且导电通孔设置在密封剂中。 导电迹线设置在接触焊盘和导电通孔之间，导热通道设置在与导电通路分开的密封剂中，并且导热层设置在半导体管芯的发热区域上。 导热迹线设置在导热层和导热通道之间。 导热层，导热迹线和导热通道与半导体管芯和导电迹线的接触焊盘电隔离。 半导体封装还包括设置在密封剂上方的宽热痕迹，以及互连宽热导迹和导热层的导热材料。

公开(公告)号：US20120181673A1

公开(公告)日：2012-07-19

申请号：US13430538

申请日：2012-03-26

Applicant: Reza A. Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

Inventor： Reza A. Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

IPC: H01L21/56 ,  H01L23/28

CPC classification number: H01L23/49575 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49517 ,  H01L23/49541 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a first semiconductor die mounted to a first contact pad on a leadframe or substrate with bumps. A conductive pillar is formed over a second semiconductor die. The second die is mounted over the first die by electrically connecting the conductive pillar to a second contact pad on the substrate with bumps. The second die is larger than the first die. An encapsulant is deposited over the first and second die. Alternatively, the conductive pillars are formed over the substrate around the first die. A heat sink is formed over the second die, and a thermal interface material is formed between the first and second die. An underfill material is deposited under the first semiconductor die. A shielding layer is formed between the first and second die. An interconnect structure can be formed over the second contact pad of the substrate.

Abstract translation: 半导体器件具有第一半导体管芯，其安装到具有凸块的引线框架或衬底上的第一接触焊盘。 在第二半导体管芯上形成导电柱。 通过将导电柱电连接到具有凸起的衬底上的第二接触焊盘上，将第二裸片安装在第一裸片上。 第二个模具大于第一个模具。 密封剂沉积在第一和第二模具上。 或者，导电柱形成在围绕第一管芯的基板上。 在第二管芯上形成散热器，并且在第一和第二管芯之间形成热界面材料。 在第一半导体管芯下沉积底部填充材料。 在第一和第二管芯之间形成屏蔽层。 可以在衬底的第二接触焊盘上形成互连结构。

公开(公告)号：US20120104623A1

公开(公告)日：2012-05-03

申请号：US12914878

申请日：2010-10-28

Applicant: Reza A. Pagaila ,  Yaojian Lin ,  Jun Mo Koo

Inventor： Reza A. Pagaila ,  Yaojian Lin ,  Jun Mo Koo

IPC: H01L23/06 ,  H01L21/56

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L23/13 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1515 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/8091 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655

Abstract: A semiconductor substrate has a plurality of different size recesses formed in the substrate to provide a stepped interposer. A conductive via can be formed through the stepped interposer. An insulating layer follows a contour of the stepped interposer. A conductive layer is formed over the insulating layer following the contour of the stepped interposer. A first semiconductor die is partially disposed in a first recess and electrically connected to the conductive layer. A second semiconductor die is partially disposed in a second recess and electrically connected to the conductive layer. The first semiconductor die is electrically connected to the second semiconductor die through the conductive layer. The first and second semiconductor die can be flipchip type semiconductor die. An encapsulant is deposited over the first and second semiconductor die. A portion of the stepped interposer can be removed to reduce thickness.

Abstract translation: 半导体衬底具有形成在衬底中的多个不同尺寸的凹部以提供阶梯式插入器。 可以通过阶梯式内插器形成导电通孔。 绝缘层遵循阶梯式插入器的轮廓。 在阶梯式插入件的轮廓之后，在绝缘层之上形成导电层。 第一半导体管芯部分地设置在第一凹部中并电连接到导电层。 第二半导体管芯部分地设置在第二凹部中并电连接到导电层。 第一半导体管芯通过导电层与第二半导体管芯电连接。 第一和第二半导体管芯可以是倒装芯片型半导体管芯。 密封剂沉积在第一和第二半导体管芯上。 可以去除部分阶梯式内插器以减小厚度。

公开(公告)号：US20120061822A1

公开(公告)日：2012-03-15

申请号：US12878661

申请日：2010-09-09

Applicant: Reza A. Pagaila

Inventor： Reza A. Pagaila

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L21/561 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10175 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/8114 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/06558 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/381 ,  H01L2224/81 ,  H01L2224/45099 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2924/0665 ,  H01L2224/05099 ,  H01L2924/00 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012

Abstract: A semiconductor device has a base substrate with first and second etch-resistant conductive layers formed over opposing surfaces of the base substrate. First cavities are etched in the base substrate through an opening in the first conductive layer. The first cavities have a width greater than a width of the opening in the first conductive layer. Second cavities are etched in the base substrate between portions of the first or second conductive layer. A semiconductor die is mounted over the base substrate with bumps disposed over the first conductive layer. The bumps are reflowed to electrically connect to the first conductive layer and cause bump material to flow into the first cavities. An encapsulant is deposited over the die and base substrate. A portion of the base substrate is removed down to the second cavities to form electrically isolated base leads between the first and second conductive layers.

Abstract translation: 半导体器件具有基底衬底，其具有形成在基底衬底的相对表面上的第一和第二耐蚀刻导电层。 第一腔通过第一导电层中的开口蚀刻在基底基底中。 第一空腔的宽度大于第一导电层中的开口的宽度。 第二空腔在第一或第二导电层的部分之间在基底衬底中蚀刻。 半导体管芯安装在基底衬底上，凸起设置在第一导电层上。 凸块被回流以电连接到第一导电层并且引起凸块材料流入第一腔。 密封剂沉积在管芯和基底衬底上。 基底衬底的一部分被去除到第二腔，以在第一和第二导电层之间形成电隔离的底部引线。

公开(公告)号：US20120056312A1

公开(公告)日：2012-03-08

申请号：US12874787

申请日：2010-09-02

Applicant: Reza A. Pagaila ,  Yaojian Lin ,  Seung Uk Yoon

Inventor： Reza A. Pagaila ,  Yaojian Lin ,  Seung Uk Yoon

IPC: H01L23/28 ,  H01L21/56

CPC classification number: H01L23/481 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/48 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/24225 ,  H01L2224/25171 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a TSV semiconductor wafer with a cavity formed in a first surface of the wafer. A second cavity can be formed in a second surface of the wafer. A plurality of semiconductor die is mounted within the cavities. The semiconductor die can be mounted side-by-side and/or stacked within the cavity. Conductive TSV can be formed through the die. An encapsulant is deposited within the cavity over the die. A CTE of the die is similar to a CTE of the encapsulant. A first interconnect structure is formed over a first surface of the encapsulant and wafer. A second interconnect structure is formed over a second surface of the encapsulant and wafer. The first and second interconnect structure are electrically connected to the TSV wafer. A second semiconductor die can be mounted over the first interconnect structure with encapsulant deposited over the second die.

Abstract translation: 半导体器件具有在晶片的第一表面中形成有腔的TSV半导体晶片。 可以在晶片的第二表面中形成第二空腔。 多个半导体管芯安装在空腔内。 半导体管芯可以并排安装和/或堆叠在腔内。 可以通过模具形成导电TSV。 密封剂沉积在模具内的空腔内。 模具的CTE类似于密封剂的CTE。 在密封剂和晶片的第一表面上形成第一互连结构。 在密封剂和晶片的第二表面上形成第二互连结构。 第一和第二互连结构电连接到TSV晶片。 第二半导体管芯可以安装在第一互连结构上，并且封装在第二管芯上。

公开(公告)号：US20120034777A1

公开(公告)日：2012-02-09

申请号：US13273537

申请日：2011-10-14

Applicant: Reza A. Pagaila ,  Zigmund R. Camacho ,  Lionel Chien Hui Tay ,  Byung Tai Do

Inventor： Reza A. Pagaila ,  Zigmund R. Camacho ,  Lionel Chien Hui Tay ,  Byung Tai Do

IPC: H01L21/768

CPC classification number: H01L21/6835 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/12 ,  H01L24/13 ,  H01L24/19 ,  H01L24/25 ,  H01L24/28 ,  H01L24/81 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/19 ,  H01L2224/24011 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/82039 ,  H01L2224/9202 ,  H01L2224/92244 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2224/83005

Abstract: A semiconductor package includes a semiconductor wafer having a plurality of semiconductor die. A contact pad is formed over and electrically connected to an active surface of the semiconductor die. A gap is formed between the semiconductor die. An insulating material is deposited in the gap between the semiconductor die. An adhesive layer is formed over a surface of the semiconductor die and the insulating material. A via is formed in the insulating material and the adhesive layer. A conductive material is deposited in the via to form a through hole via (THV). A conductive layer is formed over the contact pad and the THV to electrically connect the contact pad and the THV. The plurality of semiconductor die is singulated. The insulating material can include an organic material. The active surface of the semiconductor die can include an optical device.

Abstract translation: 半导体封装包括具有多个半导体管芯的半导体晶片。 接触垫形成在半导体管芯的有源表面上并电连接到半导体管芯的有源表面。 在半导体管芯之间形成间隙。 绝缘材料沉积在半导体管芯之间的间隙中。 在半导体管芯和绝缘材料的表面上形成粘合剂层。 在绝缘材料和粘合剂层中形成通孔。 导电材料沉积在通孔中以形成通孔（THV）。 在接触焊盘和THV上形成导电层，以电连接接触焊盘和THV。 多个半导体管芯被切割。 绝缘材料可以包括有机材料。 半导体管芯的有源表面可以包括光学器件。

公开(公告)号：US20120012990A1

公开(公告)日：2012-01-19

申请号：US12837562

申请日：2010-07-16

Applicant: Reza A. Pagaila ,  DaeSik Choi ,  Jun Mo Koo

Inventor： Reza A. Pagaila ,  DaeSik Choi ,  Jun Mo Koo

IPC: H01L23/552 ,  H01L21/60

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/34 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L24/19 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06102 ,  H01L2224/06181 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/221 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/73207 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. A shielding layer is formed between the first and second semiconductor die. An electrical interconnect, such as conductive pillar, bump, or bond wire, is formed between the first and second semiconductor die. A conductive TSV can be formed through the first and second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and electrical interconnect. A heat sink is formed over the second semiconductor die. An interconnect structure, such as a bump, can be formed over the second semiconductor die. A portion of a backside of the first semiconductor die is removed. A protective layer is formed over exposed surfaces of the first semiconductor die. The protective layer covers the exposed backside and sidewalls of the first semiconductor die.

Abstract translation: 半导体晶片具有多个第一半导体管芯。 第二半导体管芯安装到第一半导体管芯。 在第一和第二半导体管芯之间形成屏蔽层。 在第一和第二半导体管芯之间形成诸如导电柱，凸起或接合线的电互连。 可以通过第一和第二半导体管芯形成导电TSV。 密封剂沉积在第一和第二半导体管芯和电互连上。 在第二半导体管芯上形成散热器。 可以在第二半导体管芯上形成诸如凸块的互连结构。 去除第一半导体管芯的背面的一部分。 在第一半导体管芯的暴露表面上形成保护层。 保护层覆盖第一半导体管芯的暴露的背面和侧壁。

公开(公告)号：US08097490B1

公开(公告)日：2012-01-17

申请号：US12870696

申请日：2010-08-27

Applicant: Reza A. Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

Inventor： Reza A. Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

IPC: H01L21/00 ,  H01L21/4763 ,  H01L21/44

CPC classification number: H01L23/5386 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/83 ,  H01L2924/00012

Abstract: A semiconductor die has a first semiconductor die mounted to a carrier. A plurality of conductive pillars is formed over the carrier around the first die. An encapsulant is deposited over the first die and conductive pillars. A first stepped interconnect layer is formed over a first surface of the encapsulant and first die. The first stepped interconnect layer has a first opening. A second stepped interconnect layer is formed over the first stepped interconnect layer. The second stepped interconnect layer has a second opening. The carrier is removed. A build-up interconnect structure is formed over a second surface of the encapsulant and first die. A second semiconductor die over the first semiconductor die and partially within the first opening. A third semiconductor die is mounted over the second die and partially within the second opening. A fourth semiconductor die is mounted over the second stepped interconnect layer.

公开(公告)号：US20110278703A1

公开(公告)日：2011-11-17

申请号：US12780295

申请日：2010-05-14

Applicant: Reza A. Pagaila ,  Jose A. Caparas ,  Pandi C. Marimuthu

Inventor： Reza A. Pagaila ,  Jose A. Caparas ,  Pandi C. Marimuthu

IPC: H01L23/552 ,  H01L21/00

CPC classification number: H01L23/60 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/03

Abstract: A semiconductor wafer has a plurality of semiconductor die separated by a saw street. The wafer is mounted to dicing tape. The wafer is singulated through the saw street to expose side surfaces of the semiconductor die. An ESD protection layer is formed over the semiconductor die and around the exposed side surfaces of the semiconductor die. The ESD protection layer can be a metal layer, encapsulant film, conductive polymer, conductive ink, or insulating layer covered by a metal layer. The ESD protection layer is singulated between the semiconductor die. The semiconductor die covered by the ESD protection layer are mounted to a temporary carrier. An encapsulant is deposited over the ESD protection layer covering the semiconductor die. The carrier is removed. An interconnect structure is formed over the semiconductor die and encapsulant. The ESD protection layer is electrically connected to the interconnect structure to provide an ESD path.

Abstract translation: 半导体晶片具有由锯条隔开的多个半导体管芯。 晶片安装在切割胶带上。 通过锯条将晶片分割，以露出半导体管芯的侧表面。 在半导体管芯上并围绕半导体管芯的暴露的侧表面形成ESD保护层。 ESD保护层可以是由金属层覆盖的金属层，密封剂膜，导电聚合物，导电油墨或绝缘层。 ESD保护层在半导体管芯之间分离。 由ESD保护层覆盖的半导体管芯被安装到临时载体上。 密封剂沉积在覆盖半导体管芯的ESD保护层上。 载体被移除。 在半导体管芯和密封剂上形成互连结构。 ESD保护层电连接到互连结构以提供ESD路径。