公开(公告)号：US20050286284A1

公开(公告)日：2005-12-29

申请号：US10882005

申请日：2004-06-29

Applicant: Sun-Teck See ,  Horng-Yee Chou ,  Charles Lee

Inventor： Sun-Teck See ,  Horng-Yee Chou ,  Charles Lee

IPC: G11C5/00 ,  G11C11/34 ,  G11C16/02

CPC classification number: G11C16/02

Abstract: Through the use of an allocation logic unit with a Flash controller, a single primary chip enable is de-multiplexed into a multiple secondary chip enables for multiple Flash memory dies or chips. In so doing, Flash storage device capacity is greatly expanded. In a first aspect, a memory package includes a plurality of memories; and an allocation logic unit coupled to the plurality of memories for receiving a single chip enable signal. The allocation logic unit de-multiplexes the single chip enable signal to a plurality of chip enable signals. Each of the plurality of chip enable signals access to one of the plurality of memories. In a second aspect, a printed circuit board (PCB) includes a Flash controller for providing at least one primary chip enable signal. The PCB also includes a plurality of Flash memory chips and at least one allocation logic unit coupled to at least a portion of the plurality of Flash memory chips and the Flash controller. The allocation logic unit receives the at least one chip enable signal and de-multiplexes the at least one chip enable signal to a plurality of secondary chip enable signals. Each of the plurality of chip enable signals controls access to one of the Flash memory chips.

Abstract translation: 通过使用具有闪存控制器的分配逻辑单元，单个主芯片使能被解复用到多个次级芯片中，使得能够用于多个闪存芯片或芯片。 这样做，Flash存储设备容量大大扩大。 在第一方面，一种存储器包括多个存储器; 以及耦合到所述多个存储器以用于接收单个芯片使能信号的分配逻辑单元。 分配逻辑单元将单芯片使能信号解复用到多个芯片使能信号。 多个芯片使能信号中的每一个访问多个存储器中的一个。 在第二方面，印刷电路板（PCB）包括用于提供至少一个主芯片使能信号的闪光控制器。 PCB还包括多个闪存芯片和耦合到多个闪存芯片和闪存控制器的至少一部分的至少一个分配逻辑单元。 所述分配逻辑单元接收所述至少一个芯片使能信号，并且将所述至少一个芯片使能信号解复用到多个次级芯片使能信号。 多个芯片使能信号中的每一个控制对闪存芯片之一的访问。

公开(公告)号：US20050276109A1

公开(公告)日：2005-12-15

申请号：US11145940

申请日：2005-06-07

Applicant: Koji Hosono ,  Koichi Fukuda

Inventor： Koji Hosono ,  Koichi Fukuda

IPC: G11C16/06 ,  G11C16/02 ,  G11C16/04 ,  G11C16/26 ,  G11C16/32 ,  G11C19/08

CPC classification number: G11C16/32 ,  G11C16/0483 ,  G11C16/26

Abstract: A semiconductor memory device comprises a driver including a first resistor, and a control signal generator including a second resistor. A storage unit is employed to store adjustment data for setting a resistance of said second resistor at a designed resistance, which is specified based on the state of the control signal actually obtained when the resistance of the second resistor is set to a certain designed value. The storage unit is referred to for stored data to switch the second resistor to control the state of the control signal. In addition, the first resistor is switched to a resistance corresponding to the resistance of the second resistor.

Abstract translation: 半导体存储器件包括具有第一电阻器的驱动器和包括第二电阻器的控制信号发生器。 存储单元用于存储调整数据，用于根据当第二电阻器的电阻被设置为某个设计值时实际获得的控制信号的状态来指定设计的电阻来设定所述第二电阻器的电阻。 存储单元用于存储数据以切换第二电阻器以控制控制信号的状态。 此外，第一电阻器被切换到对应于第二电阻器的电阻的电阻。

公开(公告)号：US20050276107A1

公开(公告)日：2005-12-15

申请号：US10958331

申请日：2004-10-06

Applicant: Hitoshi Shiga ,  Chin-Hung Wang ,  Chin Lin

Inventor： Hitoshi Shiga ,  Chin-Hung Wang ,  Chin Lin

IPC: G11C16/02 ,  G11C11/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/34

CPC classification number: G11C16/344 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/16 ,  G11C2211/5621

Abstract: A semiconductor memory device includes a memory cell array, data buffer, and column switch. The data buffer senses the potential of a bit line to determine data in a selected memory cell and hold readout data in a read. The data buffer detects both whether the whole data buffer holds “0” data and whether the whole data buffer holds “1” data. The column switch selects part of the data buffer and connects the part to a bus.

Abstract translation: 半导体存储器件包括存储单元阵列，数据缓冲器和列开关。 数据缓冲器检测位线的电位以确定所选择的存储单元中的数据并保持读取中的读出数据。 数据缓冲器检测整个数据缓冲器是否保持“0”数据以及整个数据缓冲器是否保持“1”数据。 列开关选择数据缓冲区的一部分，并将部件连接到总线。

公开(公告)号：US20050270842A1

公开(公告)日：2005-12-08

申请号：US11144792

申请日：2005-06-06

Applicant: Hiroshi Furuta ,  Kiyokazu Hashimoto

Inventor： Hiroshi Furuta ,  Kiyokazu Hashimoto

IPC: G11C16/06 ,  G11C11/34 ,  G11C16/02 ,  G11C16/08 ,  G11C16/34 ,  G11C29/00 ,  G11C29/04

CPC classification number: G11C29/50 ,  G11C11/5628 ,  G11C16/04 ,  G11C16/3454 ,  G11C16/3459 ,  G11C29/00 ,  G11C29/50004 ,  G11C29/82 ,  G11C2029/0409 ,  G11C2211/5621

Abstract: The memory device according to an embodiment of the invention prepares a reference field (reference value range) corresponding to each logical value and if the threshold value of the cell is within that field, the cell is determined to be defective and the data of the defective cell is stored in a redundant cell. Therefore, if the threshold value drops because the cell charge leaks over time, the data which is stored can be rescued. As a background operation of a normal operating, memory device performs the memory cell check and memory cell substitution in accordance with the internal addresses generated independently than external addresses. Therefore, a defective cell can be rescued without causing delay in the normal operations of memory device.

Abstract translation: 根据本发明的实施例的存储器件准备与每个逻辑值相对应的参考场（参考值范围），并且如果单元的阈值在该场内，则确定该单元是有缺陷的，并且该缺陷的数据 单元被存储在冗余单元中。 因此，如果由于电池电荷随时间泄漏而导致阈值下降，则可以挽救存储的数据。 作为正常操作的背景操作，存储器件根据独立于外部地址产生的内部地址执行存储器单元检查和存储器单元替换。 因此，可以救出缺陷单元，而不会导致存储器件的正常操作的延迟。

公开(公告)号：US20050270832A1

公开(公告)日：2005-12-08

申请号：US10929243

申请日：2004-08-30

Applicant: Eu Chu ,  Ju Mo ,  Seong Park ,  Jung Kim ,  Hyun Lim ,  Pyeong Lee ,  Ja Jeong

Inventor： Eu Chu ,  Ju Mo ,  Seong Park ,  Jung Kim ,  Hyun Lim ,  Pyeong Lee ,  Ja Jeong

IPC: H01L27/115 ,  G11C11/00 ,  G11C16/02 ,  H01L27/24

CPC classification number: G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

Abstract: The present invention relates generally to a phase change memory device and, more particularly, to a phase change memory cell array suitable for the implementation of a high-density memory device. The phase change memory cell array includes a first access transistor pair and a second access transistor pair formed on a semiconductor substrate to be adjacent to each other while each of the first and second access transistor pairs having a common drain, phase change resistance elements formed on source regions of the access transistors, respectively, and a semiconductor region formed on the same plane as the common drains to electrically connect the common drains of the first and second transistor pairs. The phase change memory cell array and the memory device of the present invention are suitable for the implementation of a high-density semiconductor device, and capable of improving the reliability of a contact forming process by securing a sufficient space for the contact forming process.

Abstract translation: 本发明一般涉及一种相变存储器件，更具体地，涉及一种适用于实现高密度存储器件的相变存储单元阵列。 相变存储单元阵列包括形成在半导体衬底上以彼此相邻的第一存取晶体管对和第二存取晶体管对，而第一和第二存取晶体管对中的每一个具有共同的漏极，相变电阻元件形成在 分别与存取晶体管的源极区以及形成在与公共漏极相同的平面上的半导体区域以电连接第一和第二晶体管对的公共漏极。 本发明的相变存储单元阵列和存储器件适用于高密度半导体器件的实现，并且通过确保用于接触形成工艺的足够空间能够提高接触形成工艺的可靠性。

公开(公告)号：US06972997B2

公开(公告)日：2005-12-06

申请号：US10743783

申请日：2003-12-24

Applicant: Tetsuya Ishimaru ,  Nozomu Matsuzaki ,  Hitoshi Kume

Inventor： Tetsuya Ishimaru ,  Nozomu Matsuzaki ,  Hitoshi Kume

IPC: G11C11/34 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C16/0433 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/518 ,  H01L29/792

Abstract: Characteristics of a nonvolatile semiconductor memory device are improved. The memory cell comprises: an ONO film constituted by a silicon nitride film SIN for accumulating charge and by oxide films BOTOX and TOPOX disposed thereon and thereunder; a memory gate electrode MG disposed at an upper portion thereof; a select gate electrode SG disposed at a side portion thereof through the ONO film; a gate oxide film SGOX disposed thereunder. By applying a potential to a select gate electrode SG of a memory cell having a source region MS and a drain region MD and to the source region MS and by accelerating electrons flowing in a channel through a high electric field produced between a channel end of the select transistor and an end of an n-type doped region ME disposed under the memory gate electrode MG, hot holes are generated by impact ionization, and the hot holes are injected into a silicon nitride film SIN by a negative potential applied to the memory gate electrode MG, and thereby an erase operation is performed.

Abstract translation: 提高了非易失性半导体存储器件的特性。 存储单元包括：由用于累积电荷的氮化硅膜SIN和其上设置的氧化膜BOTOX和TOPOX构成的ONO膜; 设置在其上部的存储栅极电极MG; 通过ONO膜设置在其侧部的选择栅电极SG; 设置在其下方的栅氧化膜SGOX。 通过向具有源极区域MS和漏极区域MD的存储单元的选择栅极SG施加电位，并且通过在通道的沟道端之间产生的高电场加速在沟道中流动的电子， 选择晶体管和设置在存储栅电极MG下方的n型掺杂区ME的端部，通过冲击电离产生热孔，并且通过施加到存储栅的负电位将热孔注入氮化硅膜SIN 电极MG，从而进行擦除操作。

公开(公告)号：US20050265114A1

公开(公告)日：2005-12-01

申请号：US11197588

申请日：2005-08-05

Applicant: Toshihiro Tanaka ,  Yutaka Shinagawa ,  Kazufumi Suzukawa ,  Masamichi Fujito ,  Takashi Yamaki ,  Kiichi Makuta ,  Masashi Wada ,  Yoshiki Kawajiri

Inventor： Toshihiro Tanaka ,  Yutaka Shinagawa ,  Kazufumi Suzukawa ,  Masamichi Fujito ,  Takashi Yamaki ,  Kiichi Makuta ,  Masashi Wada ,  Yoshiki Kawajiri

IPC: G11C16/02 ,  G11C8/02 ,  G11C16/12

CPC classification number: G11C16/3459 ,  G11C16/12 ,  G11C2216/14

Abstract: Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.

Abstract translation: 公开了一种具有缩短的总写入时间的非易失性存储器，能够通过使写入电流恒定而稳定地写入数据，同时减少由升压电路产生的电压的波动。 在诸如闪速存储器的非易失性存储器中，在写入操作时确定数据。 在跳过对应于具有逻辑“1”（或逻辑“0”）的写入数据的位时，对与具有逻辑“0”（或逻辑“1”的写入数据相对应的位进行写操作）。

公开(公告)号：US20050265072A1

公开(公告)日：2005-12-01

申请号：US10856547

申请日：2004-05-28

Applicant: Mark Hart ,  Chung Lam ,  Christie Marrian ,  Gary McClelland ,  Simone Raoux ,  Charles Rettner ,  Hemantha Wickramasinghe

Inventor： Mark Hart ,  Chung Lam ,  Christie Marrian ,  Gary McClelland ,  Simone Raoux ,  Charles Rettner ,  Hemantha Wickramasinghe

IPC: G11C11/00 ,  G11C16/02 ,  H01L27/24

CPC classification number: H01L27/24 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/008 ,  G11C2213/72 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/124 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/1666

Abstract: A method and structure for a memory cell comprising a phase change material; a heating element in thermal contact with the phase change material, wherein the heating element is adapted to induce a phase change in the phase change material; and electrical lines configured to pass current through the heating element, wherein the phase change material and the heating element are arranged in a configuration other than being electrically connected in series. The memory cell further comprises a sensing element in thermal contact with the phase change material, wherein the sensing element is adapted to detect a change in at least one physical property of the phase change material, wherein the sensing element is adapted to detect a change in a thermal conductivity of the phase change material.

Abstract translation: 一种包括相变材料的存储单元的方法和结构; 与所述相变材料热接触的加热元件，其中所述加热元件适于引起所述相变材料的相变; 以及配置为使电流通过所述加热元件的电线，其中所述相变材料和所述加热元件被布置成不是串联电连接的构造。 存储单元还包括与相变材料热接触的感测元件，其中感测元件适于检测相变材料的至少一个物理特性的变化，其中感测元件适于检测相变材料的变化 相变材料的导热性。

公开(公告)号：US06967896B2

公开(公告)日：2005-11-22

申请号：US10354188

申请日：2003-01-30

Applicant: Shai Eisen ,  Roni Varkony ,  Mori Edan

Inventor： Shai Eisen ,  Roni Varkony ,  Mori Edan

IPC: G11C11/41 ,  G11C16/02 ,  G11C16/10 ,  G11C16/26 ,  G11C8/00 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/26

Abstract: A method for operating a memory cell array, the method comprising assigning word lines of a memory cell array as addresses for writing sets of data thereto from a cache memory, and scrambling addresses of the sets of data by writing a first chunk of the particular set of data from the cache memory to a first word line of the array, and writing a second chunk of the particular set of data from the cache memory to a second word line of the array, the first chunk comprising a first subset of the particular set of data and the second chunk comprising a second subset of the particular set of data.

Abstract translation: 一种用于操作存储单元阵列的方法，所述方法包括：将存储单元阵列的字线作为从高速缓冲存储器写入数据集的地址，以及通过写入所述特定组的第一块来对所述数据集进行加扰的地址 从高速缓冲存储器到数组的第一字线的数据，以及将来自高速缓冲存储器的特定数据组的第二块写入阵列的第二字线，第一块包括特定组的第一子集 的数据，并且所述第二块包括所述特定数据集合的第二子集。

公开(公告)号：US06967868B2

公开(公告)日：2005-11-22

申请号：US10845314

申请日：2004-05-14

Applicant: In-Young Kim ,  June Lee ,  Oh-Suk Kwon

Inventor： In-Young Kim ,  June Lee ,  Oh-Suk Kwon

IPC: G11C16/02 ,  G11C5/02 ,  G11C11/34 ,  G11C16/06 ,  G11C29/00

CPC classification number: G11C29/846 ,  G11C29/781 ,  G11C2029/1802

Abstract: A flash memory device may include: a plurality of main bit lines; a plurality of redundant bit lines; a plurality of first page buffers respectively organized as a plurality of first page buffer groups which are connected to main bit lines; a plurality of second page buffers respectively organized as a plurality of second page buffer groups which are connected to the redundant bit lines; each of the first and second page buffers including an output P/F terminal to provide pass/fail data; a plurality of fuses corresponding to the pluralities of the first and second page buffer groups, respectively, each of the fuses having one end commonly connected to the P/F terminals in a corresponding page buffer group and the other end connected to a signal line; and a pass/fail check circuit to determine an overall pass/fail signal based upon a signal on the signal line.

Abstract translation: 闪存器件可以包括：多个主位线; 多个冗余位线; 分别组织成连接到主位线的多个第一页缓冲器组的多个第一页缓冲器; 多个第二页缓冲器分别被组织为连接到冗余位线的多个第二页缓冲器组; 第一和第二页缓冲器中的每一个包括用于提供通过/不合格数据的输出P / F端子; 分别对应于多个第一和第二寻呼缓冲器组的多个保险丝，每个保险丝的一端在对应的页缓冲器组中共同连接到P / F端子，另一端连接到信号线; 以及通过/失败检查电路，以基于信号线上的信号确定总体通过/失败信号。