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    NONVOLATILE SEMICONDUCTOR MEMORY
    1.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY 审中-公开
    非易失性半导体存储器

    公开(公告)号：US20120218819A1

    公开(公告)日：2012-08-30

    申请号：US13305988

    申请日：2011-11-29

    申请人： Masataka KATO ,  Tetsuo ADACHI ,  Toshihiro TANAKA ,  Toshio SASAKI ,  Hitoshi KUME ,  Katsutaka KIMURA

    发明人： Masataka KATO ,  Tetsuo ADACHI ,  Toshihiro TANAKA ,  Toshio SASAKI ,  Hitoshi KUME ,  Katsutaka KIMURA

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0416 ,  G11C8/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

    摘要： Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

    摘要翻译： 公开了一种非易失性存储器系统，包括至少一个非易失性存储器，每个非易失性存储器具有多个非易失性存储单元和缓冲存储器; 以及耦合到所述非易失性存储器的控制装置。 控制装置能够接收外部数据并将数据应用于非易失性存储器，并且使非易失性存储器能够操作程序操作，包括将接收到的数据存储到缓冲存储器并将保存在缓冲存储器中的数据存储到缓冲存储器中 的非易失性存储单元。 此外，控制装置能够在非易失性存储器在程序操作中操作时接收外部数据。 此外，缓冲存储器能够接收与程序运行一次要存储的数据的数据长度相等的数据单位，数据长度大于1字节。

    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20120135548A1

    公开(公告)日：2012-05-31

    申请号：US13366329

    申请日：2012-02-05

    申请人： SATORU HANZAWA ,  Hitoshi Kume ,  Motoyasu Terao ,  Tomonori Sekiguchi ,  Makoto Saen

    发明人： SATORU HANZAWA ,  Hitoshi Kume ,  Motoyasu Terao ,  Tomonori Sekiguchi ,  Makoto Saen

    IPC分类号： H01L21/66

    CPC分类号： G01R31/31715 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/71 ,  G11C2213/72 ,  Y10T29/49169

    摘要： A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.

    摘要翻译： 实现了高度可靠的大容量相变存储器模块。 根据本发明的半导体器件包括具有堆叠使用硫属化物材料的存储层和由二极管构成的存储单元的结构的存储器阵列，并且根据层来改变初始化条件和重写条件 其中所选择的存储器单元被定位。 根据操作选择电流镜电路，并且同时根据电压选择中的复位电流的控制机构的操作来改变初始化条件和重写条件（这里为复位条件） 电路和电流镜电路。

    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08094489B2

    公开(公告)日：2012-01-10

    申请号：US13112567

    申请日：2011-05-20

    申请人： Satoru Hanzawa ,  Hitoshi Kume

    发明人： Satoru Hanzawa ,  Hitoshi Kume

    IPC分类号： G11C11/00 ,  G11C5/02 ,  G11C5/06 ,  G11C7/22 ,  G11C8/00

    CPC分类号： G11C13/0023 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/0083 ,  G11C2213/71 ,  G11C2213/72

    摘要： A phase change memory capable of highly reliable operations is provided. A semiconductor device has a memory array having a structure in which memory cells are stacked including memory layers using a chalcogenide material and diodes, and initialization conditions and write conditions are changed according to the layer in which a selected memory cell is positioned. The initialization conditions and write conditions (herein, reset conditions) are changed according to the operation by selecting a current mirror circuit according to the operation and by a control mechanism of a reset current in a voltage select circuit and the current mirror circuit.

    摘要翻译： 提供了具有高度可靠的操作的相变存储器。 半导体器件具有存储器阵列，其具有使用硫族化物材料和二极管层叠存储层的存储单元的结构，并且根据所选择的存储单元所在的层来改变初始化条件和写入条件。 初始化条件和写入条件（这里是复位条件）根据操作通过根据操作选择电流镜电路和通过电压选择电路和电流镜电路中的复位电流的控制机构而改变。

    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20110110150A1

    公开(公告)日：2011-05-12

    申请号：US13008893

    申请日：2011-01-18

    申请人： SATORU HANZAWA ,  Hitoshi Kume ,  Motoyasu Terao ,  Tomonori Sekiguchi ,  Makoto Sean

    发明人： SATORU HANZAWA ,  Hitoshi Kume ,  Motoyasu Terao ,  Tomonori Sekiguchi ,  Makoto Sean

    IPC分类号： G11C11/00

    CPC分类号： G01R31/31715 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/71 ,  G11C2213/72 ,  Y10T29/49169

    摘要： A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.

    摘要翻译： 实现了高度可靠的大容量相变存储器模块。 根据本发明的半导体器件包括具有堆叠使用硫属化物材料的存储层和由二极管构成的存储单元的结构的存储器阵列，并且根据层来改变初始化条件和重写条件 其中所选择的存储器单元被定位。 根据操作选择电流镜电路，并且同时根据电压选择中的复位电流的控制机构的操作来改变初始化条件和重写条件（这里为复位条件） 电路和电流镜电路。

    NONVOLATILE SEMICONDUCTOR MEMORY
    5.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY 失效
    非易失性半导体存储器

    公开(公告)号：US20110051515A1

    公开(公告)日：2011-03-03

    申请号：US12791177

    申请日：2010-06-01

    申请人： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

    发明人： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

    IPC分类号： G11C16/10 ,  G11C16/04

    CPC分类号： G11C16/0416 ,  G11C8/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

    摘要： Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

    摘要翻译： 公开了一种非易失性存储器系统，包括至少一个非易失性存储器，每个非易失性存储器具有多个非易失性存储单元和缓冲存储器; 以及耦合到所述非易失性存储器的控制装置。 控制装置能够接收外部数据并将数据应用于非易失性存储器，并且使非易失性存储器能够操作程序操作，包括将接收到的数据存储到缓冲存储器并将保存在缓冲存储器中的数据存储到缓冲存储器中 的非易失性存储单元。 此外，控制装置能够在非易失性存储器在程序操作中操作时接收外部数据。 此外，缓冲存储器能够接收与程序运行一次要存储的数据的数据长度相等的数据单位，数据长度大于1字节。

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20100058127A1

    公开(公告)日：2010-03-04

    申请号：US12469778

    申请日：2009-05-21

    申请人： Motoyasu TERAO ,  Satoru HANZAWA ,  Hitoshi KUME ,  Minoru OGUSHI ,  Yoshitaka SASAGO ,  Masaharu KINOSHITA ,  Norikatsu TAKAURA

    发明人： Motoyasu TERAO ,  Satoru HANZAWA ,  Hitoshi KUME ,  Minoru OGUSHI ,  Yoshitaka SASAGO ,  Masaharu KINOSHITA ,  Norikatsu TAKAURA

    IPC分类号： G06F11/26

    CPC分类号： G11C13/0064 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50008 ,  G11C2013/0054 ,  G11C2213/72

    摘要： To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.

    摘要翻译： 为了实现低功耗的快速且高度可靠的相变存储器系统，半导体器件包括：存储器件，其包括具有包括多个第一存储器单元的第一区域的第一存储器阵列和包括多个第一存储器单元的第二区域 第二存储单元; 控制器，其耦合到所述存储器设备以向所述存储器设备发出命令; 以及用于存储多个试写条件的条件表。 控制器基于存储在条件表中的多个试写条件，在多个第二存储单元中执行多次尝试写入，并且基于试写的结果来确定多个第一存储单元中的写入条件。 存储器件基于从控制器指示的写入条件在多个第一存储器单元中执行写入。

    Nonvolatile semiconductor memory device
    9.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US07099199B2

    公开(公告)日：2006-08-29

    申请号：US10837593

    申请日：2004-05-04

    申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

    摘要： A nonvolatile memory apparatus which includes plural memories one of which is a nonvolatile memory such as a Flash EEPROM capable of being specified a plurality of operations from a processing unit of the apparatus including an erase operation, the erase operation in the nonvolatile memory performs a threshold voltage moving operation and a verify operation, and the nonvolatile memory is capable of releasing the I/O bus during the erase operation to thereby allow accessing of other memories and/or system components. For example, during this erase operation, the Flash EEPROM is able to free the I/O data terminal such that the EEPROM becomes electrically isolated from the CPU. The CPU is then able to perform data processing by the system bus where information can then be transferred/received such as between other memories, e.g., ROM and RAM, and otherwise with the I/O port.

    摘要翻译： 一种非易失性存储装置，包括多个存储器，其中一个是诸如闪存EEPROM的非易失性存储器，其能够从包括擦除操作的装置的处理单元指定多个操作，所述非易失性存储器中的擦除操作执行阈值 电压移动操作和验证操作，并且非易失性存储器能够在擦除操作期间释放I / O总线，从而允许访问其他存储器和/或系统组件。 例如，在擦除操作期间，闪存EEPROM能够释放I / O数据终端，使得EEPROM与CPU电隔离。 CPU然后能够执行系统总线的数据处理，其中可以在诸如ROM和RAM等其他存储器之间传输/接收信息，否则可以与I / O端口进行数据处理。

    Nonvolatile semiconductor memory device
    10.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US06972997B2

    公开(公告)日：2005-12-06

    申请号：US10743783

    申请日：2003-12-24

    申请人： Tetsuya Ishimaru ,  Nozomu Matsuzaki ,  Hitoshi Kume

    发明人： Tetsuya Ishimaru ,  Nozomu Matsuzaki ,  Hitoshi Kume

    IPC分类号： G11C11/34 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G11C16/0433 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/518 ,  H01L29/792

    摘要： Characteristics of a nonvolatile semiconductor memory device are improved. The memory cell comprises: an ONO film constituted by a silicon nitride film SIN for accumulating charge and by oxide films BOTOX and TOPOX disposed thereon and thereunder; a memory gate electrode MG disposed at an upper portion thereof; a select gate electrode SG disposed at a side portion thereof through the ONO film; a gate oxide film SGOX disposed thereunder. By applying a potential to a select gate electrode SG of a memory cell having a source region MS and a drain region MD and to the source region MS and by accelerating electrons flowing in a channel through a high electric field produced between a channel end of the select transistor and an end of an n-type doped region ME disposed under the memory gate electrode MG, hot holes are generated by impact ionization, and the hot holes are injected into a silicon nitride film SIN by a negative potential applied to the memory gate electrode MG, and thereby an erase operation is performed.

    摘要翻译： 提高了非易失性半导体存储器件的特性。 存储单元包括：由用于累积电荷的氮化硅膜SIN和其上设置的氧化膜BOTOX和TOPOX构成的ONO膜; 设置在其上部的存储栅极电极MG; 通过ONO膜设置在其侧部的选择栅电极SG; 设置在其下方的栅氧化膜SGOX。 通过向具有源极区域MS和漏极区域MD的存储单元的选择栅极SG施加电位，并且通过在通道的沟道端之间产生的高电场加速在沟道中流动的电子， 选择晶体管和设置在存储栅电极MG下方的n型掺杂区ME的端部，通过冲击电离产生热孔，并且通过施加到存储栅的负电位将热孔注入氮化硅膜SIN 电极MG，从而进行擦除操作。