公开(公告)号：US08618523B2

公开(公告)日：2013-12-31

申请号：US12302740

申请日：2006-05-31

Applicant: Norikatsu Takaura ,  Yuichi Matsui ,  Motoyasu Terao ,  Yoshihisa Fujisaki ,  Nozomu Matsuzaki ,  Kenzo Kurotsuchi ,  Takahiro Morikawa

Inventor： Norikatsu Takaura ,  Yuichi Matsui ,  Motoyasu Terao ,  Yoshihisa Fujisaki ,  Nozomu Matsuzaki ,  Kenzo Kurotsuchi ,  Takahiro Morikawa

IPC: H01L47/00

CPC classification number: G11C13/0004 ,  G11C8/08 ,  G11C13/0028 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

Abstract: On an insulating film (41) in which a plug (43) as a lower electrode is embedded, a laminated layer pattern of an insulating film (51) made of tantalum oxide, a recording layer (52) made of Ge—Sb—Te based chalcogenide to which indium is introduced and an upper electrode film (53) made of tungsten or tungsten alloy is formed, thereby forming a phase change memory. By interposing the insulating film (51) between the recording layer (52) and the plug (43), an effect of reducing programming current of a phase change memory and an effect of preventing peeling of the recording layer (52) can be achieved. Further, by using the Ge—Sb—Te based chalcogenide to which indium is introduced as the recording layer (52), the difference in work function between the insulating film (51) and the recording layer (52) is increased, and the programming voltage of the phase change memory can be reduced.

Abstract translation: 在嵌入作为下电极的插头（43）的绝缘膜（41）上，由氧化钽构成的绝缘膜（51）的叠层图案，由Ge-Sb-Te制成的记录层（52） 引入铟的硫属化合物和由钨或钨合金制成的上电极膜（53），从而形成相变存储器。 通过将绝缘膜（51）插入在记录层（52）和插塞（43）之间，可以实现降低相变存储器的编程电流的效果和防止记录层（52）的剥离的效果。 此外，通过使用引入了铟的Ge-Sb-Te类硫族化物作为记录层（52），绝缘膜（51）和记录层（52）之间的功函数差增大，编程 可以减小相变存储器的电压。

公开(公告)号：US08546783B2

公开(公告)日：2013-10-01

申请号：US13541097

申请日：2012-07-03

Applicant: Masahiro Moniwa ,  Nozomu Matsuzaki ,  Riichiro Takemura

Inventor： Masahiro Moniwa ,  Nozomu Matsuzaki ,  Riichiro Takemura

IPC: H01L31/032 ,  H01L45/00

CPC classification number: H01L45/144 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

Abstract: A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration and using a phase change film as a memory element. Between a MISFET of a region forming one memory cell and an adjoining MISFET, each MISFET source adjoins in the front surface of an insulating semiconductor substrate. A multi-layer structure of a phase change film and electric conduction film of specific resistance lower than the specific resistance is formed in plan view of the front surface of a semiconductor substrate ranging over each source of both MISFETs, and a plug is stacked thereon. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of the semiconductor substrate, and an electric conduction film sends current in a parallel direction on the surface of the semiconductor substrate.

Abstract translation: 实现了容易形成相变膜的半导体器件及其制造方法，实现了高集成度和使用相变膜作为存储元件。 在形成一个存储单元的区域的MISFET与相邻的MISFET之间，每个MISFET源在绝缘半导体衬底的前表面相邻。 在两个MISFET的每个源极上的半导体衬底的前表面的平面图中形成具有比电阻率低的电阻率的相变膜和导电膜的多层结构，并且在其上层叠插塞。 多层结构用作在半导体衬底的表面上平行延伸并存在的布线，并且导电膜在半导体衬底的表面上沿平行方向发送电流。

公开(公告)号：US20120241715A1

公开(公告)日：2012-09-27

申请号：US13493442

申请日：2012-06-11

Applicant: YUICHI MATSUI ,  Nozomu Matsuzaki ,  Norikatsu Takaura ,  Naoki Yamamoto ,  Hideyuki Matsuoka ,  Tomio Iwasaki

Inventor： YUICHI MATSUI ,  Nozomu Matsuzaki ,  Norikatsu Takaura ,  Naoki Yamamoto ,  Hideyuki Matsuoka ,  Tomio Iwasaki

IPC: H01L27/26 ,  H01L47/00

CPC classification number: H01L45/06 ,  H01L27/2436 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

Abstract: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.

公开(公告)号：US08000126B2

公开(公告)日：2011-08-16

申请号：US12522744

申请日：2007-01-11

Applicant: Takahiro Morikawa ,  Motoyasu Terao ,  Norikatsu Takaura ,  Kenzo Kurotsuchi ,  Nozomu Matsuzaki ,  Yoshihisa Fujisaki ,  Masaharu Kinoshita ,  Yuichi Matsui

Inventor： Takahiro Morikawa ,  Motoyasu Terao ,  Norikatsu Takaura ,  Kenzo Kurotsuchi ,  Nozomu Matsuzaki ,  Yoshihisa Fujisaki ,  Masaharu Kinoshita ,  Yuichi Matsui

IPC: G11C11/00 ,  H01L29/66

CPC classification number: H01L45/144 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

Abstract: A phase change memory is formed of a plug buried within a through-hole in an insulating film formed on a semiconductor substrate, an interface layer formed on the insulating film in which the plug is buried, a recording layer formed of a chalcogenide layer formed on the interface layer, and an upper contact electrode formed on the recording layer. The recording layer storing information according to resistance value change is made of chalcogenide material containing indium in an amount range from 20 atomic % to 38 atomic %, germanium in a range from 9 atomic % to 28 atomic %, antimony in a range from 3 atomic % to 18 atomic %, and tellurium in a range from 42 atomic % to 63 atomic %, where the content of germanium larger than or equal to the content of antimony.

Abstract translation: 相变存储器由形成在半导体衬底上的绝缘膜中的埋入通孔内的插塞形成，形成在绝缘膜上的界面层，其中埋入插塞，由硫化物层形成的记录层形成在 界面层和形成在记录层上的上接触电极。 根据电阻值变化存储信息的记录层由含有20原子％至38原子％的量的铟的含量为9原子％至28原子％的锗的硫属化物材料制成，3原子级的锑 ％〜18原子％，碲为42原子％〜63原子％，锗的含量大于或等于锑的含量。

公开(公告)号：US20110049454A1

公开(公告)日：2011-03-03

申请号：US12305890

申请日：2006-06-23

Applicant: Motoyasu Terao ,  Yuichi Matsui ,  Tsuyoshi Koga ,  Nozomu Matsuzaki ,  Norikatsu Takaura ,  Yoshihisa Fujisaki ,  Kenzo Kurotsuchi ,  Takahiro Morikawa ,  Yoshitaka Sasago ,  Junko Ushiyama ,  Akemi Hirotsune

Inventor： Motoyasu Terao ,  Yuichi Matsui ,  Tsuyoshi Koga ,  Nozomu Matsuzaki ,  Norikatsu Takaura ,  Yoshihisa Fujisaki ,  Kenzo Kurotsuchi ,  Takahiro Morikawa ,  Yoshitaka Sasago ,  Junko Ushiyama ,  Akemi Hirotsune

IPC: H01L45/00

CPC classification number: H01L45/1675 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144

Abstract: In a phase-change memory, an interface layer is inserted between a chalcogenide material layer and a plug. The interface layer is arranged so as not to cover the entire interface of a plug-like electrode. When the plug is formed at an upper part than the chalcogenide layer, the degree of integration is increased. The interface layer is formed by carrying out sputtering using an oxide target, or, by forming a metal film by carrying out sputtering using a metal target followed by oxidizing the metal film in an oxidation atmosphere such as oxygen radical, oxygen plasma, etc.

Abstract translation: 在相变存储器中，界面层插入硫族化物材料层和插塞之间。 界面层被布置成不覆盖插塞状电极的整个界面。 当塞子形成在比硫族化物层的上部时，积分度增加。 通过使用氧化物靶进行溅射而形成界面层，或者通过使用金属靶进行溅射而形成金属膜，然后在氧自由基，氧等离子体等的氧化气氛中氧化金属膜。

公开(公告)号：US07796426B2

公开(公告)日：2010-09-14

申请号：US12090375

申请日：2005-10-17

Applicant: Osamu Tonomura ,  Norikatsu Takaura ,  Kenzo Kurotsuchi ,  Nozomu Matsuzaki

Inventor： Osamu Tonomura ,  Norikatsu Takaura ,  Kenzo Kurotsuchi ,  Nozomu Matsuzaki

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C7/04 ,  G11C13/0004 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/79

Abstract: A technique capable of improving speed of a set operation, which controls writing rate in a semiconductor device including a memory cell using a phase-change material. The technique uses means for setting a set-pulse voltage to be applied to the phase-change material to have two steps: the first-step voltage sets a temperature of the phase-change memory to a temperature at which the fastest nucleation is obtained; and the second pulse sets the temperature to a temperature at which the fastest crystal growth is obtained, thereby obtaining solid-phase growth of the phase-change material without melting. Moreover, the technique uses means for controlling the two-step voltage applied to the phase-change memory by a two-step voltage applied to a word line capable of reducing the drain current variation.

Abstract translation: 一种能够提高设定操作速度的技术，其控制包括使用相变材料的存储单元的半导体器件的写入速度。 该技术使用用于设定要施加到相变材料的设定脉冲电压的装置以具有两个步骤：第一步骤电压将相变存储器的温度设置为获得最快成核的温度; 并且第二脉冲将温度设定为获得最快的晶体生长的温度，从而获得相变材料的固相生长而不熔化。 此外，该技术使用用于通过施加到能够减小漏极电流变化的字线的两级电压来控制施加到相变存储器的两级电压的装置。

公开(公告)号：US07692234B2

公开(公告)日：2010-04-06

申请号：US11862928

申请日：2007-09-27

Applicant: Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

Inventor： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

IPC: H01L29/788

CPC classification number: H01L21/28273 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3454 ,  H01L21/28061 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833

Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

Abstract translation: 一种半导体器件，其特别是确保器件的可靠性，特别是在微细的区域中并且能够实现大的电容和高速操作，具有在半导体衬底的主表面的第一区域中包括栅绝缘膜，浮栅电极， 层间绝缘膜，控制栅极电极以及以矩阵形式布置的第二导电类型的源极和漏极区域，具有用于隔离存储单元的浅隔离结构。 当使用用绝缘膜掩埋的浅结构用于元件隔离时，可以防止微细区域中的隔离耐受电压降低，并且可以降低选择性晶体管的阈值电平的变化。 当通过选择性晶体管分配存储器垫中的存储单元时，可以提高存储单元的干扰电阻。

公开(公告)号：US20090189136A1

公开(公告)日：2009-07-30

申请号：US12359594

申请日：2009-01-26

Applicant: Nozomu Matsuzaki

Inventor： Nozomu Matsuzaki

IPC: H01L29/43 ,  H01L21/71 ,  H01L21/336

CPC classification number: H01L45/1233 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

Abstract: A reliability of a semiconductor device having a phase-change memory is improved. A phase-change memory device has a bottom-electrode plug buried in an interlayer insulator that is provided on a main surface of a semiconductor substrate, an electric conductive material layer provided on an upper portion of the bottom-electrode plug and on the interlayer insulator, a phase-change material layer provided on the electric conductive material layer, and an upper-electrode plug provided on the phase-change material layer. The bottom-electrode plug and the upper-electrode plug which configure the phase-change memory device are provided at respective different positions in a plane of the semiconductor substrate.

Abstract translation: 提高了具有相变存储器的半导体器件的可靠性。 相变存储器件具有掩埋在半导体衬底的主表面上的层间绝缘体中的底电极插塞，设置在底电极插塞的上部和层间绝缘体上的导电材料层 设置在导电材料层上的相变材料层和设置在相变材料层上的上电极插塞。 配置相变存储器件的底电极插头和上电极插头设置在半导体衬底的平面中的各个不同位置处。

公开(公告)号：US07528036B2

公开(公告)日：2009-05-05

申请号：US11107826

申请日：2005-04-18

Applicant: Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

Inventor： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

IPC: H01L21/336

CPC classification number: H01L21/28273 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3454 ,  H01L21/28061 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833

Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

公开(公告)号：US20080297220A1

公开(公告)日：2008-12-04

申请号：US12153385

申请日：2008-05-19

Applicant: Nozomu Matsuzaki ,  Hiroyuki Mizuno ,  Masashi Horiguchi

Inventor： Nozomu Matsuzaki ,  Hiroyuki Mizuno ,  Masashi Horiguchi

IPC: H03K3/356

CPC classification number: H01L21/823857 ,  B82Y99/00 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/0883 ,  H01L29/42364 ,  Y10S438/981 ,  Y10S977/936

Abstract: The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.