知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

49 条记录 (耗时 0.026 秒)

    Semiconductor element and process for manufacturing the same
    1.
    发明申请
    Semiconductor element and process for manufacturing the same 审中-公开
    半导体元件及其制造方法

    公开(公告)号：US20050032276A1

    公开(公告)日：2005-02-10

    申请号：US10936481

    申请日：2004-09-09

    申请人： Tomoyuki Ishii ,  Kazuo Yano ,  Koichi Seki ,  Toshiyuki Mine ,  Takashi Kobayashi

    发明人： Tomoyuki Ishii ,  Kazuo Yano ,  Koichi Seki ,  Toshiyuki Mine ,  Takashi Kobayashi

    IPC分类号： H01L27/115 ,  H01L27/12 ,  H01L29/68 ,  H01L29/788 ,  H01L21/00 ,  H01L21/82 ,  H01L21/8236

    CPC分类号： H01L29/7887 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/685 ,  H01L29/7883 ,  Y10S438/962

    摘要： A semiconductor quantum memory element is disclosed which can share the terminals easily among a plurality of memory elements and can pass a high current and which is strong against noises. In order to accomplish this a control electrode is formed so as to cover the entirety of thin film regions connecting low-resistance regions. As a result, the element can have a small size and can store information with high density. Thus, a highly integrated, low power consumption non-volatile memory device can be realized with reduced size. A method of forming a memory element is also disclosed including performing the following steps of forming a first insulating layer, a second insulating layer, a first conductive layer and a layer of amorphous silicon. The amorphous silicon layer is crystallized to a polycrystalline silicon film. Semiconductor drains are deposited to form charge trapping and storage regions. A fourth insulating layer is deposited over the drains and a second conductive layer is deposited over a layer of silicon dioxide to form a control electrode of the memory element.

    摘要翻译： 公开了一种半导体量子存储器元件，其可以容易地在多个存储元件之间共享端子，并且可以通过高电流并且抵抗噪声。 为了实现这一点，形成控制电极以覆盖连接低电阻区域的整个薄膜区域。 因此，该元件可以具有小尺寸并且可以高密度地存储信息。 因此，可以以减小的尺寸实现高度集成的低功耗非易失性存储器件。 还公开了一种形成存储元件的方法，包括执行以下步骤：形成第一绝缘层，第二绝缘层，第一导电层和非晶硅层。 非晶硅层结晶成多晶硅膜。 沉积半导体漏极以形成电荷捕获和存储区域。 在漏极上沉积第四绝缘层，并且在二氧化硅层上沉积第二导电层以形成存储元件的控制电极。

    Nonvolatile semiconductor memory device
    3.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US6157576A

    公开(公告)日：2000-12-05

    申请号：US393301

    申请日：1999-09-10

    申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    IPC分类号： G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  G11C16/04

    CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

    摘要： Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.

    摘要翻译： 在具有其中电可擦除非易失性存储元件以矩阵形式布置的存储器阵列的EEPROM中，包括擦除控制电路，其在执行擦除操作之后在对应的存储器单元上至少执行一次读出操作 根据外部提供的擦除操作指令。 擦除操作由内部擦除控制电路自动执行，同时响应于来自微处理器的指令，EEPROM与微处理器电隔离。 微处理器的控制只需要稍微短的时间段，在擦除操作期间EEPROM保留在系统中时，指令擦除开始。 在本发明的一个方面中，将Vcc电源施加到每个非易失性半导体存储单元的源极区域或漏极区域，并且将具有与Vcc电源的极性相反的极性的擦除电压施加到控制栅极 电极。 擦除电压被提供给设置在非易失性存储器件内的电压转换电路。 因此，可以通过Vcc单电源实现擦除操作。 此外，响应于每个存储元件的单独擦除速度，对于每个存储元件或每个集合存储元件单独控制集体擦除操作的实质端子。

    Semiconductor integrated circuit
    4.
    发明授权
    Semiconductor integrated circuit 有权

    公开(公告)号：US6049232A

    公开(公告)日：2000-04-11

    申请号：US225291

    申请日：1999-01-05

    申请人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

    发明人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

    IPC分类号： G06F17/50 ,  H03K19/173 ,  H03K19/0948

    CPC分类号： H03K19/1736 ,  G06F17/505 ,  H03K19/1737

    摘要： For the relation between the first and second pass-transistor circuits (PT1, PT2), the output signal of the preceding-stage is supplied to the gate of the succeeding-stage, and for the relation between the second and third pass-transistor circuits (PT2, PT3), the output signal of the preceding-stage is supplied to the source-drain path of the succeeding-stage. The first pass-transistor circuit (PT1) receives on its first input node (In1) and second input node (In2) the first input signal and the second input signal that are logically independent from each other. This logic circuit requires a smaller number of transistors and is capable of reducing the power consumption and delay and accomplishing an intricate logic function.

    Nonvolatile semiconductor memory device
    5.
    发明授权
    Nonvolatile semiconductor memory device 失效

    公开(公告)号：US5781476A

    公开(公告)日：1998-07-14

    申请号：US456797

    申请日：1995-06-01

    申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    IPC分类号： G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  G11C11/34

    CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

    摘要： Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.

    Logic circuit sythesizing method utilizing binary decision diagram explored based upon hierarchy of correlation between input variables
    6.
    发明授权
    Logic circuit sythesizing method utilizing binary decision diagram explored based upon hierarchy of correlation between input variables 失效
    基于输入变量之间相关性层次的二元决策图的逻辑电路协调方法

    公开(公告)号：US5712792A

    公开(公告)日：1998-01-27

    申请号：US633486

    申请日：1996-04-17

    申请人： Shunzo Yamashita ,  Kazuo Yano ,  Yasuhiko Sasaki ,  Koichi Seki

    发明人： Shunzo Yamashita ,  Kazuo Yano ,  Yasuhiko Sasaki ,  Koichi Seki

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505

    摘要： In order to effectively explore a binary decision diagram for synthesizing a logic circuit, a tentative circuit comprised of AND gates and OR gates is synthesized from a logic function. The number of gates in this circuit to which two input variables are simultaneously associated are counted and used as correlation between the two input variables. A correlation matrix for correlation among all of the input variables is generated. The input variables are sequentially grouped from a set of input variables with strongest correlation in the correlation matrix: These groups are registered into a correlation tree, and an intergroup correlation tree is produced. These groups are sequentially selected from a group with the least correlation, and the intragroup order of the selected group is changed from one to another. A binary decision diagram is explored which satisfies the most appropriate condition in that group (such as the minimum number of nodes, the minimum delay, and the minimum area). The above processes repeated for all groups. Each node of the binary decision diagram thus obtained is substituted by a selector and each selector circuit is substituted by a circuit of a transistor level.

    摘要翻译： 为了有效地研究用于合成逻辑电路的二进制判定图，从逻辑功能合成了由与门和或门组成的暂定电路。 两个输入变量同时关联的该电路中的门数被计数并用作两个输入变量之间的相关。 生成所有输入变量之间相关的相关矩阵。 输入变量从相关矩阵中具有最强相关性的一组输入变量顺序分组：将这些组注册到相关树中，并产生一个组间相关树。 从具有最小相关性的组中顺序地选择这些组，并且所选择的组的组内顺序从一个改变为另一组。 探讨了满足该组中最合适条件（如最小节点数，最小延迟和最小面积）的二进制决策图。 上述过程对所有组重复。 由此获得的二进制判定图的每个节点由选择器代替，并且每个选择器电路被晶体管电平的电路代替。

    Mobile communication end device with low power operation mode
    8.
    发明授权
    Mobile communication end device with low power operation mode 失效
    移动通信终端设备具有低功耗操作模式

    公开(公告)号：US5623533A

    公开(公告)日：1997-04-22

    申请号：US621896

    申请日：1996-03-26

    申请人： Takafumi Kikuchi ,  Yuji Hatano ,  Koichi Seki ,  Masanori Otsuka ,  Masao Hotta ,  Yasuyuki Murakami

    发明人： Takafumi Kikuchi ,  Yuji Hatano ,  Koichi Seki ,  Masanori Otsuka ,  Masao Hotta ,  Yasuyuki Murakami

    IPC分类号： H04B1/16 ,  H04W52/00 ,  H04Q7/32

    CPC分类号： H04W52/029 ,  Y02B60/50

    摘要： In a mobile wireless communication end device having an electric power source including a cell, and a signal processing part and a transmitting-receiving part, to which electric power is applied from the electric power source, operation is performed in operation mode selected previously by the user when voltage of the electric power source is dropped. The signal processing part and the transmitting-receiving part have a normal operation mode operating at normal electric power and a low power operation mode operating at electric power lower than the normal operation mode. The mobile wireless communication end device includes operation mode setting apparatus for previously setting the operation mode of the device, observing apparatus for observing the voltage of the cell of the electric power source and generating a low power operation request signal when the voltage becomes a prescribed value or less, and apparatus for changing the signal processing part and the transmitting-receiving part to low power operation mode, when the low power operation mode is set by the operation mode setting means and the low power operation request signal is generated by the observing apparatus.

    摘要翻译： 在具有包括单元的电源的移动无线通信终端装置以及从电源向其施加电力的信号处理部和发送接收部，在以前由 用户当电源的电压下降时。 信号处理部分和发送接收部分具有在正常工作模式下操作的正常操作模式和低于正常操作模式的电力操作的低功率操作模式。 移动无线通信终端装置包括用于预先设定装置的操作模式的操作模式设置装置，用于观察电源单元的电压的观察装置，并且当电压变为规定值时产生低功率操作请求信号 以及当由操作模式设置装置设置低功率操作模式并且由观察装置产生低功率操作请求信号时，将信号处理部分和发送接收部分改变为低功率操作模式的装置 。