公开(公告)号：US07309892B2

公开(公告)日：2007-12-18

申请号：US11439152

申请日：2006-05-24

Applicant: Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

Inventor： Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

IPC: H01L29/76 ,  H01L29/788 ,  H01L29/94

CPC classification number: B82Y10/00 ,  G11C11/22 ,  G11C11/404 ,  G11C16/02 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/28 ,  G11C2216/06 ,  G11C2216/08 ,  H01L21/28273 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11551 ,  H01L27/1203 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7613 ,  H01L29/785 ,  H01L29/7888

Abstract: A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.

Abstract translation: 一种场效应半导体元件，其具有较少数量的元件和减小的面积，并能够自身存储数据，而不需要在低温下进行冷却;以及采用该半导体元件的存储器件。 栅极沟道电容被设置得如此小，以致捕获捕获一个电子或空穴是否可以根据半导体FET元件的电流的变化来明确且明显地被检测。 通过检测通过在陷阱中捕获电子或空穴而导致的半导体元件的阈值电压的变化，可以在室温下实现数据存储。

公开(公告)号：US07061053B2

公开(公告)日：2006-06-13

申请号：US10929424

申请日：2004-08-31

Applicant: Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

Inventor： Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

IPC: H01L29/76

CPC classification number: B82Y10/00 ,  G11C11/22 ,  G11C11/404 ,  G11C16/02 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/28 ,  G11C2216/06 ,  G11C2216/08 ,  H01L21/28273 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11551 ,  H01L27/1203 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7613 ,  H01L29/785 ,  H01L29/7888

Abstract: A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.

公开(公告)号：US5615145A

公开(公告)日：1997-03-25

申请号：US580090

申请日：1995-12-20

Applicant: Kan Takeuchi ,  Katsumi Matsuno ,  Kazuhiko Kajiyama ,  Osamu Nagashima ,  Masatoshi Hasegawa

Inventor： Kan Takeuchi ,  Katsumi Matsuno ,  Kazuhiko Kajiyama ,  Osamu Nagashima ,  Masatoshi Hasegawa

IPC: G11C11/22 ,  G11C14/00 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108

CPC classification number: G11C11/22

Abstract: A semiconductor memory which includes a plurality of memory cells each having first and second capacitors connected in series and a field-effect transistor whose source or drain is connected to a node between the first and second capacitors. The memory cells are arranged at intersections of bit lines and word lines thereby forming a matrix. The first capacitor of each memory cell is a ferroelectric capacitor using a ferroelectric material as an insulating film. A plate electrode of the first capacitor of each memory cell is held at a first potential when the memory is operated in a first mode and the plate electrode of the first capacitor is held at a second potential when the memory is operated in a second mode. The first potential is different from the second potential.

Abstract translation: 一种半导体存储器，包括多个存储单元，每个存储单元均具有串联连接的第一和第二电容器，以及源极或漏极连接到第一和第二电容器之间的节点的场效应晶体管。 存储单元布置在位线和字线的交点处，从而形成矩阵。 每个存储单元的第一电容器是使用铁电材料作为绝缘膜的铁电电容器。 当存储器以第一模式操作时，每个存储单元的第一电容器的平板电极被保持在第一电位，并且当存储器在第二模式下操作时，第一电容器的平板电极被保持在第二电位。 第一个潜力与第二个潜力不同。

公开(公告)号：US5455786A

公开(公告)日：1995-10-03

申请号：US257542

申请日：1994-06-09

Applicant: Kan Takeuchi ,  Katsumi Matsuno ,  Yoshinobu Nakagome ,  Masakazu Aoki

Inventor： Kan Takeuchi ,  Katsumi Matsuno ,  Yoshinobu Nakagome ,  Masakazu Aoki

IPC: H01L27/10 ,  G11C11/22 ,  G11C14/00 ,  H01L21/8246 ,  H01L27/105

CPC classification number: G11C11/22

Abstract: A highly reliable and high speed ferroelectric memory having high degree of integration is provided. In a ferroelectric memory having a plurality of memory cells M1 each constituted by one transistor and one ferroelectric capacitor. In the normal operation, the ferroelectric memory is used as a volatile memory in which a voltage of a storage node ST1 is utilized as the stored information. Both an electric potential at a plate PL1 of the ferroelectric capacitor and a precharge electric potential on a data line DL1(j) are made Vcc/2.

Abstract translation: 提供了具有高集成度的高可靠性和高速铁电存储器。 在具有由一个晶体管和一个铁电电容器构成的多个存储单元M1的铁电存储器中。 在正常操作中，铁电存储器用作其中使用存储节点ST1的电压作为存储信息的易失性存储器。 铁电电容器的板PL1上的电位和数据线DL1（j）上的预充电电位都为Vcc / 2。

公开(公告)号：US5266848A

公开(公告)日：1993-11-30

申请号：US674602

申请日：1991-03-25

Applicant: Yoshinobu Nakagome ,  Kiyoo Itoh ,  Kan Takeuchi

Inventor： Yoshinobu Nakagome ,  Kiyoo Itoh ,  Kan Takeuchi

IPC: H03K19/0948 ,  H03K3/356 ,  H03K19/00 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/17 ,  H03K19/092

CPC classification number: H03K3/356113 ,  H03K19/0013 ,  H03K19/01721 ,  H03K19/018521 ,  H03K3/356017

Abstract: A CMOS circuit has a signal receiving unit, a signal processing unit and a driving circuit. The signal receiving unit converts a small amplitude signal from a bus into a large amplitude signal. The signal processing unit processes the large amplitude signal. The driving circuit converts the large amplitude signal processed into a small amplitude signal processed to output on the bus.

Abstract translation: CMOS电路具有信号接收单元，信号处理单元和驱动电路。 信号接收单元将来自总线的小振幅信号转换为大振幅信号。 信号处理单元处理大振幅信号。 驱动电路将被处理的大振幅信号转换成处理成在总线上输出的小振幅信号。

公开(公告)号：US07786585B2

公开(公告)日：2010-08-31

申请号：US12188591

申请日：2008-08-08

Applicant: Takako Funakoshi ,  Eiichi Murakami ,  Kazumasa Yanagisawa ,  Kan Takeuchi ,  Hideo Aoki ,  Hizuru Yamaguchi ,  Takayuki Oshima ,  Kazuyuki Tsunokuni ,  Kousuke Okuyama

Inventor： Takako Funakoshi ,  Eiichi Murakami ,  Kazumasa Yanagisawa ,  Kan Takeuchi ,  Hideo Aoki ,  Hizuru Yamaguchi ,  Takayuki Oshima ,  Kazuyuki Tsunokuni ,  Kousuke Okuyama

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L23/53238 ,  H01L21/823871 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.

Abstract translation: 在具有多层埋地布线的半导体集成电路装置中，旨在防止在其底部连接到埋地布线的插头与埋地布线之间的界面处的应力迁移引起的不连续性的发生。 例如，在第一Cu布线的宽度不小于约0.9μm且小于约1.44μm的情况下，并且第二Cu布线的宽度和塞子的直径为约0.18μm的情况下，存在 布置两个或更多个将第一布线和第二铜布线彼此电连接的插头。

公开(公告)号：US06787841B2

公开(公告)日：2004-09-07

申请号：US10650732

申请日：2003-08-29

Applicant: Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

Inventor： Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

IPC: H01L2976

CPC classification number: B82Y10/00 ,  G11C11/22 ,  G11C11/404 ,  G11C16/02 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/28 ,  G11C2216/06 ,  G11C2216/08 ,  H01L21/28273 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11551 ,  H01L27/1203 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7613 ,  H01L29/785 ,  H01L29/7888

Abstract: A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.

Abstract translation: 一种场效应半导体元件，其具有较少数量的元件和减小的面积，并能够自身存储数据，而不需要在低温下进行冷却;以及采用该半导体元件的存储器件。 栅极沟道电容被设置得如此小，以致捕获捕获一个电子或空穴是否可以根据半导体FET元件的电流的变化来明确且明显地被检测。 通过检测通过在陷阱中捕获电子或空穴而导致的半导体元件的阈值电压的变化，可以在室温下实现数据存储。

公开(公告)号：US06555882B2

公开(公告)日：2003-04-29

申请号：US09943444

申请日：2001-08-31

Applicant: Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

Inventor： Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

IPC: H01L2976

CPC classification number: B82Y10/00 ,  G11C11/22 ,  G11C11/404 ,  G11C16/02 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/28 ,  G11C2216/06 ,  G11C2216/08 ,  H01L21/28273 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11551 ,  H01L27/1203 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7613 ,  H01L29/785 ,  H01L29/7888

Abstract: A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.

公开(公告)号：US06477090B2

公开(公告)日：2002-11-05

申请号：US09939708

申请日：2001-08-28

Applicant: Takashi Yamaki ,  Kan Takeuchi ,  Mitsuru Hiraki ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Masamichi Fujito

Inventor： Takashi Yamaki ,  Kan Takeuchi ,  Mitsuru Hiraki ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Masamichi Fujito

IPC: G11C700

CPC classification number: G11C29/50008 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/28 ,  G11C16/30 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

Abstract: A semiconductor device whose characteristics are highly reliably regulated for circuits whose desired characteristics need to be realized without being affect by unevenness in device characteristics is to be provided. A replica MOS transistor for amperage measurement connected to an external measuring terminal is provided. A delay circuit and other circuits whose desired characteristics are to be realized have a constant current source MOS transistor formed in the same process as the replica MOS transistor, and a trimming voltage vtri is commonly applied to the respective gates of the constant current source MOS transistor and the replica MOS transistor. Trimming data determined on the basis of an amperage measured from the external measuring terminal are stored into a memory means such as an electrically rewritable non-volatile memory or the like. The trimming data determine the trimming voltage vtri.

Abstract translation: 提供一种其特性对于其所需特性需要实现而不受设备特性不均匀影响的电路高度可靠地调节的半导体器件。 提供连接到外部测量端子的用于安培数测量的复制MOS晶体管。 要实现其期望特性的延迟电路和其它电路具有与复制MOS晶体管相同的工艺形成的恒流源MOS晶体管，并且微调电压vtri通常施加到恒流源MOS晶体管的各个栅极 和复制MOS晶体管。 基于从外部测量终端测量的电流强度确定的修整数据被存储到诸如电可重写非易失性存储器等的存储装置中。 修整数据确定修整电压vtri。

公开(公告)号：US6104056A

公开(公告)日：2000-08-15

申请号：US126437

申请日：1998-07-30

Applicant: Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

Inventor： Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

IPC: H01L21/8247 ,  G11C11/22 ,  G11C11/404 ,  G11C16/02 ,  G11C16/04 ,  G11C16/28 ,  H01L21/28 ,  H01L21/336 ,  H01L27/01 ,  H01L27/115 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/76 ,  H01L29/788 ,  H01L29/792 ,  H01L29/94 ,  H01L31/036 ,  H01L31/062 ,  H01L31/112 ,  H01L31/113 ,  H01L21/119

CPC classification number: B82Y10/00 ,  G11C11/22 ,  G11C11/404 ,  G11C16/02 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/28 ,  H01L21/28273 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11551 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7613 ,  H01L29/7888 ,  G11C2216/06 ,  G11C2216/08 ,  H01L27/1203 ,  H01L29/785

Abstract: A field-effect semiconductor element implemented with a reduced number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature. In accordance with one embodiment, a carrier confinement region, isolated from a channel and a gate of the semiconductor FET element, is provided to operate as a storage node for trapping the carrier or carriers.

Abstract translation: 一种场效应半导体元件，其具有减少的元件数量和减少的面积，并且能够自身存储数据，而不需要在低温下进行冷却;以及采用该半导体元件的存储器件。 栅极沟道电容被设置得如此小，以致捕获捕获一个电子或空穴是否可以根据半导体FET元件的电流的变化来明确且明显地被检测。 通过检测通过在陷阱中捕获电子或空穴而导致的半导体元件的阈值电压的变化，可以在室温下实现数据存储。 根据一个实施例，提供了从沟道分离的载流子限制区域和半导体FET元件的栅极，以用作捕获载体或载流子的存储节点。