公开(公告)号：US08017986B2

公开(公告)日：2011-09-13

申请号：US12718111

申请日：2010-03-05

Applicant: Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

Inventor： Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

IPC: H01L29/788

CPC classification number: G11C16/26 ,  G11C5/025 ,  G11C8/08 ,  G11C16/04 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H01L21/28 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7885 ,  H01L29/792

Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc

Abstract translation: 半导体器件包括多个非易失性存储单元（1）。 每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。 第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。 第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。 第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。 假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

公开(公告)号：US07821824B2

公开(公告)日：2010-10-26

申请号：US12258964

申请日：2008-10-27

Applicant: Yutaka Shinagawa ,  Takeshi Kataoka ,  Eiichi Ishikawa ,  Toshihiro Tanaka ,  Kazumasa Yanagisawa ,  Kazufumi Suzukawa

Inventor： Yutaka Shinagawa ,  Takeshi Kataoka ,  Eiichi Ishikawa ,  Toshihiro Tanaka ,  Kazumasa Yanagisawa ,  Kazufumi Suzukawa

IPC: G11C16/04

CPC classification number: G11C16/349 ,  G11C16/06 ,  G11C16/3495

Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information.

Abstract translation: 半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写的非易失性存储区域。 非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。 第一非易失性存储区具有用于存储大于第二非易失性存储区的信息的阈值电压的最大变化宽度。 当用于存储信息的阈值电压的最大变化幅度较大时，由于由于存储信息的重写操作而对存储单元的应力变大，所以在保证重写操作次数方面较差; 然而，由于读取电流变大，因此可以加快存储器信息的读取速度。 优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以对第二非易失性存储器区域进行优先排列以保证存储器信息的重写操作的次数。

公开(公告)号：US07447959B2

公开(公告)日：2008-11-04

申请号：US11785537

申请日：2007-04-18

Applicant: Toshihiro Tanaka ,  Yutaka Shinagawa ,  Masahiko Kimura ,  Isao Nakamura

Inventor： Toshihiro Tanaka ,  Yutaka Shinagawa ,  Masahiko Kimura ,  Isao Nakamura

IPC: G01R31/28 ,  G06K5/04

CPC classification number: G11C29/021 ,  G01R31/30 ,  G01R31/31703 ,  G01R31/31725 ,  G01R31/3187 ,  G06F11/24 ,  G11C16/04 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2029/5004

Abstract: A semiconductor integrated circuit (LSI) in which control information for determining a voltage or a width of a pulse produced itself can easily be set in parallel with other LSIs, and set information can be corrected easily. From an external evaluation device, a voltage of an expected value is supplied in overlapping manner to a plurality of LSIs each having a CPU and a flash memory. Each LSI incorporates a comparison circuit comparing an expected voltage value and a boosted voltage generated in itself. The CPU refers to a comparison result and optimizes control data in a data register for changing a boosted voltage. The CPU controls the comparison circuit and the data register and performs trimming in a self-completion manner, thereby making, trimming on a plurality of LSIs easily in a parallel manner and a total test time reduced.

Abstract translation: 其中可以容易地与其他LSI并行设置用于确定其本身产生的脉冲的电压或宽度的控制信息的半导体集成电路（LSI），并且可以容易地校正设置信息。 从外部评估装置，将预期值的电压重叠地提供给具有CPU和闪速存储器的多个LSI。 每个LSI包含比较电路，其比较期望的电压值和本身产生的升压电压。 CPU参考比较结果并优化用于改变升压电压的数据寄存器中的控制数据。 CPU控制比较电路和数据寄存器，并且以自完成方式进行修整，从而以并行方式容易地对多个LSI进行修整，并且总的测试时间减少。

公开(公告)号：US07414283B2

公开(公告)日：2008-08-19

申请号：US11415129

申请日：2006-05-02

Applicant: Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

Inventor： Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

IPC: H01L29/788

CPC classification number: G11C16/26 ,  G11C5/025 ,  G11C8/08 ,  G11C16/04 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H01L21/28 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7885 ,  H01L29/792

Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc

Abstract translation: 半导体器件包括多个非易失性存储单元（1）。 每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。 第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。 第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。 第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。 假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

公开(公告)号：US20060044871A1

公开(公告)日：2006-03-02

申请号：US11195684

申请日：2005-08-03

Applicant: Hiroyuki Tanikawa ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Takashi Yamaki

Inventor： Hiroyuki Tanikawa ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Takashi Yamaki

IPC: G11C16/06

CPC classification number: G11C16/344

Abstract: The present invention is directed to realize both higher reading speed and assurance of the larger number of rewriting times for a nonvolatile memory. A semiconductor integrated circuit has a first nonvolatile memory area and a second nonvolatile memory area for storing information in accordance with a threshold voltage which varies. One or plural conditions out of erase verify determination memory gate voltage, erase verify determination memory current, write verify determination memory gate voltage, write verify determination memory current, erase voltage, erase voltage application time, write voltage, and write voltage application time in the first nonvolatile memory area is/are made different from that/those in the second nonvolatile memory area, speed of reading information stored in the first nonvolatile memory area is higher than that of reading information stored in the second nonvolatile memory area, and the assured number of rewriting times in the second nonvolatile memory area is larger than that in the first nonvolatile memory area.

Abstract translation: 本发明旨在实现更高的读取速度和对非易失性存储器的更大数量的重写时间的保证。 半导体集成电路具有第一非易失性存储区域和用于根据变化的阈值电压存储信息的第二非易失性存储区域。 擦除验证存储器栅极电压，擦除验证确定存储器电流，写入验证确定存储器栅极电压，写入验证确定存储器电流，擦除电压，擦除电压施加时间，写入电压和写入电压施加时间中的一个或多个条件 第一非易失性存储器区域与第二非易失性存储区域中的那些不同，第一非易失性存储区域中存储的读取信息的速度高于存储在第二非易失性存储区域中的读取信息的速度，并且确定的数量 在第二非易失性存储器区域中的重写次数大于第一非易失性存储器区域中的重写时间。

公开(公告)号：US06963507B2

公开(公告)日：2005-11-08

申请号：US10419228

申请日：2003-04-21

Applicant: Toshihiro Tanaka ,  Yutaka Shinagawa ,  Kazufumi Suzukawa ,  Masamichi Fujito ,  Takashi Yamaki ,  Kiichi Makuta ,  Masashi Wada ,  Yoshiki Kawajiri

Inventor： Toshihiro Tanaka ,  Yutaka Shinagawa ,  Kazufumi Suzukawa ,  Masamichi Fujito ,  Takashi Yamaki ,  Kiichi Makuta ,  Masashi Wada ,  Yoshiki Kawajiri

IPC: G11C16/02 ,  G11C8/02 ,  G11C16/12 ,  G11C16/04

CPC classification number: G11C16/3459 ,  G11C16/12 ,  G11C2216/14

Abstract: Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.

公开(公告)号：US06747895B2

公开(公告)日：2004-06-08

申请号：US10083602

申请日：2002-02-27

Applicant: Yukiko Umemoto ,  Toshihiro Tanaka ,  Hiroyuki Tanikawa ,  Yutaka Shinagawa

Inventor： Yukiko Umemoto ,  Toshihiro Tanaka ,  Hiroyuki Tanikawa ,  Yutaka Shinagawa

IPC: G11C1604

CPC classification number: G11C16/3445 ,  G11C8/12 ,  G11C16/16 ,  G11C2216/18

Abstract: This inventing is intended to shorten data deletion time of a nonvolatile semiconductor memory such as a flash memory (EEPROM). When deleting data written to a memory cell MC0 among flash memory cells MC0 to MC2 formed on a semiconductor substrate PSUB through a separation region NiSO, a voltage of p type well PWL0 in which the memory cell MC0 is formed is raised to 10V and a voltage of the separation region NiSO is raised to 12V by using a voltage application unit different from a voltage application unit applying a voltage to the p type well PWL0. As a result, parasitic capacitances Ca1 and Ca2 generated between p type wells PWL1 and PWL2 in which the unselected memory cells MC1 and MC2 are formed and the separation region NiSO, respectively, and a parasitic capacitance Cb generated between the separation region NiSO and the semiconductor substrate PSUB are charged by the voltage application units. It is, therefore, possible to shorten time required to charge the parasitic capacitances and to shorten the deletion time.

Abstract translation: 本发明旨在缩短诸如闪速存储器（EEPROM）的非易失性半导体存储器的数据删除时间。 当通过分离区域NiSO删除在半导体衬底PSUB上形成的闪存单元MC0至MC2中写入存储单元MC0的数据时，形成存储单元MC0的p型阱PWL0的电压升高到10V， 通过使用与向p型阱PWL0施加电压的电压施加单元不同的电压施加单元将NiSO升高到12V。 结果，在形成未选择的存储单元MC1和MC2的p型阱PWL1和PWL2之间分别产生的寄生电容Ca1和Ca2分别与分离区NiSO和半导体之间产生的寄生电容Cb 基板PSUB由电压施加单元充电。 因此，可以缩短为寄生电容充电所需的时间并缩短删除时间。

公开(公告)号：US08576643B2

公开(公告)日：2013-11-05

申请号：US13368461

申请日：2012-02-08

Applicant: Yutaka Shinagawa ,  Takeshi Kataoka ,  Eiichi Ishikawa ,  Toshihiro Tanaka ,  Kazumasa Yanagisawa ,  Kazufumi Suzukawa

Inventor： Yutaka Shinagawa ,  Takeshi Kataoka ,  Eiichi Ishikawa ,  Toshihiro Tanaka ,  Kazumasa Yanagisawa ,  Kazufumi Suzukawa

IPC: G11C7/00

CPC classification number: G11C16/349 ,  G11C16/06 ,  G11C16/3495

Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has a maximum variation width of a threshold voltage for memorizing an information set larger than that of the second nonvolatile memory area. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information, and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information.

Abstract translation: 半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写的非易失性存储区域。 非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。 第一非易失性存储区具有用于存储大于第二非易失性存储区的信息集的阈值电压的最大变化宽度。 可以优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以对第二非易失性存储器区域进行优先排列以保证存储器信息的重写操作的次数。

公开(公告)号：US20090129173A1

公开(公告)日：2009-05-21

申请号：US12269098

申请日：2008-11-12

Applicant: Shinya KAJIYAMA ,  Yutaka Shinagawa ,  Makoto Mizuno ,  Hideo Kasai ,  Takao Watanabe ,  Riichiro Takemura ,  Tomonori Sekiguchi

Inventor： Shinya KAJIYAMA ,  Yutaka Shinagawa ,  Makoto Mizuno ,  Hideo Kasai ,  Takao Watanabe ,  Riichiro Takemura ,  Tomonori Sekiguchi

IPC: G11C7/00 ,  G11C8/08 ,  G11C8/00 ,  G11C7/06

CPC classification number: G11C7/1039 ,  G11C7/1075 ,  G11C16/26

Abstract: The semiconductor integrated circuit device includes: a first latch which can hold an output signal of the X decoder and transfer the signal to the word driver in a post stage subsequent to the X decoder; a second latch which can hold an output signal of the Y decoder and transfer the signal to the column multiplexer in the post stage subsequent to the Y decoder; and a third latch which can hold an output signal of the sense amplifier and transfer the signal to the output buffer in the post stage subsequent to the sense amplifier. The structure makes it possible to pipeline-control a series of processes for reading data stored in the non-volatile semiconductor memory, and enables low-latency access even with access requests from CPUs conflicting.

Abstract translation: 半导体集成电路装置包括：第一锁存器，其可以保持X解码器的输出信号，并且在X解码器之后的后级中将信号传送到字驱动器; 第二锁存器，其可以保持Y解码器的输出信号，并且在Y解码器之后的后级中将信号传送到列多路复用器; 以及第三锁存器，其可以保持读出放大器的输出信号，并且在读出放大器之后的后级中将该信号传送到输出缓冲器。 该结构使得可以对一系列用于读取存储在非易失性半导体存储器中的数据的处理进行流水线控制，并且即使在来自CPU的访问请求冲突的情况下也能够进行低延迟访问。

公开(公告)号：US20090052238A1

公开(公告)日：2009-02-26

申请号：US12258964

申请日：2008-10-27

Applicant: Yutaka Shinagawa ,  Takeshi Kataoka ,  Eiichi Ishikawa ,  Toshihiro Tanaka ,  Kazumasa Yanagisawa ,  Kazufumi Suzukawa

Inventor： Yutaka Shinagawa ,  Takeshi Kataoka ,  Eiichi Ishikawa ,  Toshihiro Tanaka ,  Kazumasa Yanagisawa ,  Kazufumi Suzukawa

IPC: G11C16/00

CPC classification number: G11C16/349 ,  G11C16/06 ,  G11C16/3495

Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized in guaranteeing the number of times of rewrite operation of memory information more.

Abstract translation: 半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写的非易失性存储区域。 非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。 第一非易失性存储区具有用于存储大于第二非易失性存储区的信息的阈值电压的最大变化宽度。 当用于存储信息的阈值电压的最大变化幅度较大时，由于由于存储信息的重写操作而对存储单元的应力变大，所以在保证重写操作次数方面较差; 然而，由于读取电流变大，因此可以加快存储器信息的读取速度。 优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以优先考虑第二非易失性存储器区域，以保证存储器信息的重写操作的次数更多。