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    Non-volatile storage device
    1.
    发明授权
    Non-volatile storage device 有权
    非易失性存储设备

    公开(公告)号：US08547751B2

    公开(公告)日：2013-10-01

    申请号：US13327930

    申请日：2011-12-16

    申请人： Hiroyuki Tanikawa ,  Bunsho Kuramori

    发明人： Hiroyuki Tanikawa ,  Bunsho Kuramori

    IPC分类号： G11C11/4193 ,  G11C11/4197

    CPC分类号： G11C7/062 ,  G11C16/24 ,  G11C16/28

    摘要： There is provided a non-volatile storage device including: a bit line that is connected to a non-volatile storage element and is applied with a voltage of magnitude corresponding to the logic value stored in the storage element; a charging section that charges the bit line to a voltage of equivalent magnitude to the reference voltage; a voltage generation section that is connected between the reference voltage line and the bit line, comprises a capacitance load for generating coupling charge when charging by the charging section has been performed, and employs the capacitance load to generate a voltage according to a difference between the magnitude of the voltage of the reference voltage line and the magnitude of the voltage of the bit line as a voltage expressing the comparison result; and a charge absorbing section for absorbing the coupling charge generated by the capacitance load.

    摘要翻译： 提供了一种非易失性存储装置，包括：位线，其连接到非易失性存储元件，并施加与存储在存储元件中的逻辑值对应的大小的电压; 充电部，其将所述位线充电到与所述参考电压等价的电压; 连接在参考电压线和位线之间的电压产生部分包括用于在由充电部进行充电时产生耦合电荷的电容负载，并且采用电容负载来产生根据 参考电压线的电压的大小和位线的电压的大小作为表示比较结果的电压; 以及用于吸收由电容负载产生的耦合电荷的电荷吸收部分。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF REUSING SAME
    3.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF REUSING SAME 有权
    非易失性半导体存储器件及其相关方法

    公开(公告)号：US20120014178A1

    公开(公告)日：2012-01-19

    申请号：US13179206

    申请日：2011-07-08

    申请人： Yuji NAGASHIMA ,  Bunsho Kuramori ,  Hiroyuki Tanikawa

    发明人： Yuji NAGASHIMA ,  Bunsho Kuramori ,  Hiroyuki Tanikawa

    IPC分类号： G11C11/4195 ,  G11C11/4197

    CPC分类号： G11C8/06 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/10 ,  G11C17/146 ,  G11C29/883

    摘要： A nonvolatile semiconductor memory device and a method of reusing the same that allow a good use of the semiconductor device without degrading characteristics even when reused. The semiconductor memory device comprises information holding means for holding information that indicates an operation mode of said memory cell array, a decoder for generating, to said memory cell array, a selection signal to designate at least a read address of said memory cell array in accordance with an address signal that comprises plural bits; and mode setting means for fixing a logical value of at least one bit of said plural bits of said address signal in accordance with the information held by said information holding means, and supplying said address signal, on which fixing of the logical value is effected, to said decoder.

    摘要翻译： 一种非易失性半导体存储器件及其再利用方法，即使在再利用时也能够良好地利用半导体器件而不劣化特性。 半导体存储器件包括用于保存指示所述存储单元阵列的操作模式的信息的信息保持装置，用于向所述存储单元阵列生成至少指定所述存储单元阵列的读地址的选择信号的解码器 具有包括多个位的地址信号; 以及模式设定装置，用于根据由所述信息保持装置保存的信息来固定所述地址信号的所述多个比特的至少一个比特的逻辑值，并且提供实现该逻辑值固定的所述地址信号， 到所述解码器。

    Semiconductor integrated circuit
    4.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US07286410B2

    公开(公告)日：2007-10-23

    申请号：US11195684

    申请日：2005-08-03

    申请人： Hiroyuki Tanikawa ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Takashi Yamaki

    发明人： Hiroyuki Tanikawa ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Takashi Yamaki

    IPC分类号： G11C16/06

    CPC分类号： G11C16/344

    摘要： A semiconductor integrated circuit has a first nonvolatile memory area and a second nonvolatile memory area to store information in accordance with a variable threshold voltage. At least one condition of the following conditions of the first nonvolatile memory area is made different from that of the second nonvolatile memory area: erase verify determination memory gate voltage, erase verify determination memory current, write verify determination memory gate voltage, write verify determination memory current, erase voltage, erase voltage application time, write voltage, and write voltage application time in the first nonvolatile memory area.

    摘要翻译： 半导体集成电路具有第一非易失性存储区域和第二非易失性存储区域，用于根据可变阈值电压存储信息。 使第一非易失性存储区域的以下条件的至少一个条件与第二非易失性存储器区域的不同：擦除验证确定存储器栅极电压，擦除验证确定存储器电流，写入验证确定存储器栅极电压，写入验证确定存储器 第一非易失性存储器区域中的电流，擦除电压，擦除电压施加时间，写入电压和写入电压施加时间。

    Nonvolatile memory and semiconductor device with controlled voltage booster circuit
    7.
    发明授权
    Nonvolatile memory and semiconductor device with controlled voltage booster circuit 有权
    具有受控升压电路的非易失性存储器和半导体器件

    公开(公告)号：US06542411B2

    公开(公告)日：2003-04-01

    申请号：US09970675

    申请日：2001-10-05

    申请人： Hiroyuki Tanikawa ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Yoshiki Kawajiri ,  Masamichi Fujito

    发明人： Hiroyuki Tanikawa ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Yoshiki Kawajiri ,  Masamichi Fujito

    IPC分类号： G11C1604

    CPC分类号： G11C16/3472 ,  G11C16/30 ,  G11C16/3468 ,  G11C16/3481

    摘要： A nonvolatile memory includes a control register (CRG) for providing instructions as to basic operations such as writing, erasing, reading, etc., a boosted voltage attainment detecting circuit for detecting whether a voltage boosted by a booster circuit has reached a desired level, a circuit which counts the time required to apply each of write and erase voltages, and a circuit which detects the completion of the writing or erasing. Respective operations are automatically advanced by simple setting of the operation instructions to the control register. After the completion of the operations, an end flag (FLAG) provided within the control register is set to notify the completion of the writing or erasing.

    摘要翻译： 非易失性存储器包括用于提供关于基本操作（诸如写入，擦除，读取等）的指令的控制寄存器（CRG），用于检测由升压电路升压的电压是否达到期望水平的升压电压达到检测电路， 计算施加写入和擦除电压中的每一个所需的时间的电路，以及检测写入或擦除完成的电路。 通过将操作指令简单设置到控制寄存器，可以自动提高各自的操作。 操作完成后，设置控制寄存器内提供的结束标志（FLAG），通知写入或擦除完成。

    Nonvolatile semiconductor memory device and method of reusing same
    8.
    发明授权
    Nonvolatile semiconductor memory device and method of reusing same 有权
    非易失性半导体存储器件及其使用方法

    公开(公告)号：US08854877B2

    公开(公告)日：2014-10-07

    申请号：US13179206

    申请日：2011-07-08

    申请人： Yuji Nagashima ,  Bunsho Kuramori ,  Hiroyuki Tanikawa

    发明人： Yuji Nagashima ,  Bunsho Kuramori ,  Hiroyuki Tanikawa

    IPC分类号： G11C11/34 ,  G11C8/06 ,  G11C16/10 ,  G11C16/04 ,  G11C29/00 ,  G11C17/14

    CPC分类号： G11C8/06 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/10 ,  G11C17/146 ,  G11C29/883

    摘要： A nonvolatile semiconductor memory device and a method of reusing the same that allow a good use of the semiconductor device without degrading characteristics even when reused. The semiconductor memory device comprises information holding means for holding information that indicates an operation mode of said memory cell array, a decoder for generating, to said memory cell array, a selection signal to designate at least a read address of said memory cell array in accordance with an address signal that comprises plural bits; and mode setting means for fixing a logical value of at least one bit of said plural bits of said address signal in accordance with the information held by said information holding means, and supplying said address signal, on which fixing of the logical value is effected, to said decoder.

    摘要翻译： 一种非易失性半导体存储器件及其再利用方法，即使在再利用时也能够良好地利用半导体器件而不劣化特性。 半导体存储器件包括用于保存指示所述存储单元阵列的操作模式的信息的信息保持装置，用于向所述存储单元阵列生成至少指定所述存储单元阵列的读地址的选择信号的解码器 具有包括多个位的地址信号; 以及模式设定装置，用于根据由所述信息保持装置保存的信息来固定所述地址信号的所述多个比特的至少一个比特的逻辑值，并且提供实现该逻辑值固定的所述地址信号， 到所述解码器。