公开(公告)号：US20130141968A1

公开(公告)日：2013-06-06

申请号：US13814104

申请日：2011-08-26

申请人： Yoshitaka Sasago ,  Hiroyuki Minemura ,  Takashi Kobayashi ,  Toshimichi Shintani ,  Satoru Hanzawa ,  Masaharu Kinoshita

发明人： Yoshitaka Sasago ,  Hiroyuki Minemura ,  Takashi Kobayashi ,  Toshimichi Shintani ,  Satoru Hanzawa ,  Masaharu Kinoshita

IPC分类号： G11C13/00

CPC分类号： G11C13/0004 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/75 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233

摘要： The purpose of the present invention is to improve a rewriting transmission rate and reliability of a phase change memory. To attain the purpose, a plurality of phase change memory cells (SMC or USMC) which are provided in series between a word line (2) and a bit line (3) and have a selection element and a storage element that are parallel connected with each other are entirely set, and after that, a part of the cells corresponding to a data pattern is reset. Alternatively, the reverse of the operation is carried out.

摘要翻译： 本发明的目的是提高相变存储器的重写传输速率和可靠性。 为了实现该目的，在串行（2）和位线（3）之间串联提供多个相变存储单元（SMC或USMC），并且具有并联连接的选择元件和存储元件 彼此完全设置，之后，与数据模式对应的单元的一部分被重置。 或者，执行相反的操作。

公开(公告)号：US08289764B2

公开(公告)日：2012-10-16

申请号：US13139297

申请日：2009-12-07

申请人： Satoru Hanzawa

发明人： Satoru Hanzawa

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C7/18 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C2013/009 ,  G11C2213/71 ,  G11C2213/72

摘要： A highly-reliable, highly-integrated large-capacity phase-change memory is achieved. For this purpose, for example, memory tiles MT0, MT1 are provided respectively at points of intersection of global bit line GBL0 and global word lines GWL00B, GWL01B. Word lines WL000 of MT0, MT1 are commonly connected to an output from a word-line driving circuit WD0 which is controlled by GWL00B, and word lines WL001 of MT0, MT1 are commonly connected to an output from a word-line driving circuit WD1 controlled by GWL01B. For example, when WD0 is activated in accordance with a rewrite operation, an output from WD0 is connected to GBL0 via any one of four memory cells MC00, MC01 connected to WL000 of MT0, MT1.

摘要翻译： 实现了高度可靠，高度集成的大容量相变存储器。 为此，例如，分别在全局位线GBL0和全局字线GWL00B，GWL01B的交点处提供存储器片MT0，MT1。 MT0，MT1的字线WL000通常连接到由GWL00B控制的字线驱动电路WD0的输出，MT0，MT1的字线WL001共同连接到控制了字线驱动电路WD1的输出 由GWL01B。 例如，当根据重写操作激活WD0时，WD0的输出通过连​​接到MT0，MT1的WL000的四个存储单元MC00，MC01中的任一个连接到GBL0。

公开(公告)号：US20120137058A1

公开(公告)日：2012-05-31

申请号：US13389260

申请日：2010-06-18

申请人： Satoru Hanzawa

发明人： Satoru Hanzawa

IPC分类号： G06F12/00

CPC分类号： G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097

摘要： A high-speed large-capacity phase-change memory is achieved. A semiconductor device according to the present invention includes: a plurality of memory planes MP; a plurality of storage information register groups SDRBK paired with the plurality of memory planes; and a chip control circuit CPCTL. The plurality of memory planes include a plurality of memory cells. Also, the plurality of storage information register groups temporarily retain information to be stored in the plurality of memory planes. Further, the chip control circuit includes a register which temporarily stores a value indicating volume of the storage information, and a first storage information volume is smaller than a second storage information volume. When the first storage information volume is written, the plurality of memory planes and the plurality of storage information register groups are activated during a first period. When the second storage information volume is written, the plurality of memory planes and the plurality of storage information register groups are activated during a second period. By such a structure, the first period is shorter than the second period.

摘要翻译： 实现了高速大容量相变存储器。 根据本发明的半导体器件包括：多个存储器平面MP; 与多个存储器平面配对的多个存储信息寄存器组SDRBK; 和芯片控制电路CPCTL。 多个存储器平面包括多个存储单元。 此外，多个存储信息寄存器组临时保留要存储在多个存储器平面中的信息。 此外，芯片控制电路包括临时存储指示存储信息的卷的值的寄存器，并且第一存储信息量小于第二存储信息量。 当第一存储信息量被写入时，多个存储器平面和多个存储信息寄存器组在第一时段期间被激活。 当第二存储信息量被写入时，多个存储器平面和多个存储信息寄存器组在第二时段期间被激活。 通过这种结构，第一周期比第二周期短。

公开(公告)号：US08130575B2

公开(公告)日：2012-03-06

申请号：US13207611

申请日：2011-08-11

申请人： Satoru Hanzawa ,  Hitoshi Kume ,  Motoyasu Terao ,  Tomonori Sekiguchi ,  Makoto Saen

发明人： Satoru Hanzawa ,  Hitoshi Kume ,  Motoyasu Terao ,  Tomonori Sekiguchi ,  Makoto Saen

IPC分类号： G11C7/00 ,  G11C11/00

CPC分类号： G01R31/31715 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/71 ,  G11C2213/72 ,  Y10T29/49169

摘要： A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.

摘要翻译： 实现了高度可靠的大容量相变存储器模块。 根据本发明的半导体器件包括具有堆叠使用硫属化物材料的存储层和由二极管构成的存储单元的结构的存储器阵列，并且根据层来改变初始化条件和重写条件 其中所选择的存储器单元被定位。 根据操作选择电流镜电路，并且同时根据电压选择中的复位电流的控制机构的操作来改变初始化条件和重写条件（这里为复位条件） 电路和电流镜电路。

公开(公告)号：US20110283039A1

公开(公告)日：2011-11-17

申请号：US13191442

申请日：2011-07-26

申请人： MOTOYASU TERAO ,  Satoru Hanzawa ,  Hitoshi Kume ,  Minoru Ogushi ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Norikatsu Takaura

发明人： MOTOYASU TERAO ,  Satoru Hanzawa ,  Hitoshi Kume ,  Minoru Ogushi ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Norikatsu Takaura

IPC分类号： G06F12/06

CPC分类号： G11C13/0064 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50008 ,  G11C2013/0054 ,  G11C2213/72

摘要： To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.

摘要翻译： 为了实现低功耗的快速且高度可靠的相变存储器系统，半导体器件包括：存储器件，其包括具有包括多个第一存储器单元的第一区域的第一存储器阵列和包括多个第一存储器单元的第二区域 第二存储单元; 控制器，其耦合到所述存储器设备以向所述存储器设备发出命令; 以及用于存储多个试写条件的条件表。 控制器基于存储在条件表中的多个试写条件，在多个第二存储单元中执行多次尝试写入，并且基于试写的结果来确定多个第一存储单元中的写入条件。 存储器件基于从控制器指示的写入条件在多个第一存储器单元中执行写入。

公开(公告)号：US20110273927A1

公开(公告)日：2011-11-10

申请号：US13104005

申请日：2011-05-09

申请人： Satoru Hanzawa ,  Yoshitska Sasago

发明人： Satoru Hanzawa ,  Yoshitska Sasago

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/75 ,  G11C2213/78 ,  H01L27/2454 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/124 ,  H01L45/144

摘要： A semiconductor device has multiple memory cell groups arranged at intersections between multiple word lines and multiple bit lines intersecting the word lines. The memory cell groups each have first and second memory cells connected in series. Each of the first and the second memory cells has a select transistor and a resistive storage device connected in parallel. The gate electrode of the select transistor in the first memory cell is connected with a first gate line, and the gate electrode of the select transistor in the second memory cell is connected to a second gate line. A first circuit block for driving the word lines (word driver group WDBK) is arranged between a second circuit block for driving the first and second gate lines (phase-change-type chain cell control circuit PCCCTL) and multiple memory cell groups (memory cell array MA).

摘要翻译： 半导体器件具有布置在多个字线和与字线相交的多个位线之间的交叉处的多个存储单元组。 存储单元组各自具有串联连接的第一和第二存储器单元。 第一和第二存储单元中的每一个具有并联连接的选择晶体管和电阻存储装置。 第一存储单元中的选择晶体管的栅电极与第一栅极线连接，第二存储单元中的选择晶体管的栅电极连接到第二栅极线。 用于驱动字线的第一电路块（字驱动器组WDBK）被布置在用于驱动第一和第二栅极线（相变型链单元控制电路PCCCTL）的第二电路块和多个存储单元组 阵列MA）。

公开(公告)号：US07983109B2

公开(公告)日：2011-07-19

申请号：US12890636

申请日：2010-09-25

申请人： Satoru Hanzawa ,  Hitoshi Kume

发明人： Satoru Hanzawa ,  Hitoshi Kume

IPC分类号： G11C8/00 ,  G11C5/02 ,  G11C5/06 ,  G11C7/00

CPC分类号： G11C13/0023 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/0083 ,  G11C2213/71 ,  G11C2213/72

摘要： A phase change memory capable of highly reliable operations is provided. A semiconductor device has a memory array having a structure in which memory cells are stacked including memory layers using a chalcogenide material and diodes, and initialization conditions and write conditions are changed according to the layer in which a selected memory cell is positioned. The initialization conditions and write conditions (herein, reset conditions) are changed according to the operation by selecting a current mirror circuit according to the operation and by a control mechanism of a reset current in a voltage select circuit and the current mirror circuit.

摘要翻译： 提供了具有高度可靠的操作的相变存储器。 半导体器件具有存储器阵列，其具有使用硫族化物材料和二极管层叠存储层的存储单元的结构，并且根据所选择的存储单元所在的层来改变初始化条件和写入条件。 初始化条件和写入条件（这里是复位条件）根据操作通过根据操作选择电流镜电路和通过电压选择电路和电流镜电路中的复位电流的控制机构而改变。

公开(公告)号：US07978524B2

公开(公告)日：2011-07-12

申请号：US12862350

申请日：2010-08-24

申请人： Satoru Hanzawa ,  Takeshi Sakata

发明人： Satoru Hanzawa ,  Takeshi Sakata

IPC分类号： G11C16/06

CPC分类号： G11C29/787 ,  G11C7/14 ,  G11C11/1673 ,  G11C11/1693

摘要： A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.

摘要翻译： 虚拟单元包括多个用于存储“1”或“0”的第一存储单元MC，其布置在多个字线WR0至WR7与多个第一数据线D0至D7之间的交点处，多个第一 用于存储“1”或“0”的虚拟单元MCH，布置在字线WR0至WR7和第一虚拟数据线之间的交点处，以及多个第二虚拟单元MCL，用于存储“0” 字线WR0〜WR7与第二伪数据线DD1的交点。

公开(公告)号：US07864568B2

公开(公告)日：2011-01-04

申请号：US12516690

申请日：2006-12-07

申请人： Yoshihisa Fujisaki ,  Satoru Hanzawa ,  Kenzo Kurotsuchi ,  Nozomu Matsuzaki ,  Norikatsu Takaura

发明人： Yoshihisa Fujisaki ,  Satoru Hanzawa ,  Kenzo Kurotsuchi ,  Nozomu Matsuzaki ,  Norikatsu Takaura

IPC分类号： G11C11/00

CPC分类号： H01L45/144 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2213/75 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233

摘要： In a semiconductor storage device such as a phase change memory, a technique which can realize high integration is provided. The semiconductor storage device includes a phase change thin film 101 having two stable phases of a crystal state with low electric resistance and an amorphous state with high electric resistance, upper plug electrodes 102 and 103 provided on one side of the phase change thin film 101, a lower electrode 104 provided on the other side of the phase change thin film 101, a selecting transistor 114 whose drain/source terminals are connected to the upper plug electrode 102 and the lower electrode 104, and a selecting transistor 115 whose drain/source terminals are connected to the upper plug electrode 103 and the lower electrode 104, and a first memory cell is configured with the selecting transistor 114 and a phase change region 111 in the phase change thin film 101 sandwiched between the upper plug electrode 102 and the lower electrode 104, and a second memory cell is configured with the selecting transistor 115 and a phase change region 112 in the phase change thin film 101 sandwiched between the upper plug electrode 103 and the lower electrode 104.

摘要翻译： 在诸如相变存储器的半导体存储装置中，提供了可以实现高集成度的技术。 半导体存储装置包括：具有低电阻的晶体状态的两个稳定相和具有高电阻的非晶态的相变薄膜101，设置在相变薄膜101一侧的上部插塞电极102和103， 设置在相变薄膜101的另一侧的下部电极104，漏极/源极端子连接到上部插塞电极102和下部电极104的选择晶体管114，以及选择晶体管115，其漏极/源极端子 连接到上插头电极103和下电极104，并且第一存储单元配置有夹在上插头电极102和下电极之间的相变薄膜101中的选择晶体管114和相变区域111 104，并且第二存储单元配置有夹在b中的相变薄膜101中的选择晶体管115和相变区域112 在上塞电极103和下电极104之间。

公开(公告)号：US07830706B2

公开(公告)日：2010-11-09

申请号：US12335418

申请日：2008-12-15

申请人： Satoru Hanzawa ,  Hitoshi Kume

发明人： Satoru Hanzawa ,  Hitoshi Kume

IPC分类号： G11C11/00

CPC分类号： G11C13/0023 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/0083 ,  G11C2213/71 ,  G11C2213/72

摘要： A phase change memory capable of highly reliable operations is provided. A semiconductor device has a memory array having a structure in which memory cells are stacked including memory layers using a chalcogenide material and diodes, and initialization conditions and write conditions are changed according to the layer in which a selected memory cell is positioned. The initialization conditions and write conditions (herein, reset conditions) are changed according to the operation by selecting a current mirror circuit according to the operation and by a control mechanism of a reset current in a voltage select circuit and the current mirror circuit.

摘要翻译： 提供了具有高度可靠的操作的相变存储器。 半导体器件具有存储器阵列，其具有使用硫族化物材料和二极管层叠存储层的存储单元的结构，并且根据所选择的存储单元所在的层来改变初始化条件和写入条件。 初始化条件和写入条件（这里是复位条件）根据操作通过根据操作选择电流镜电路和通过电压选择电路和电流镜电路中的复位电流的控制机构而改变。