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公开(公告)号：US08445913B2
公开(公告)日：2013-05-21
申请号：US11980213
申请日：2007-10-30
Applicant: Steven Avanzino , Tzu-Ning Fang , Swaroop Kaza , Dongxiang Liao , Wai Lo , Christie Marrian , Sameer Haddad
Inventor： Steven Avanzino , Tzu-Ning Fang , Swaroop Kaza , Dongxiang Liao , Wai Lo , Christie Marrian , Sameer Haddad
IPC: H01L29/12
CPC classification number: H01L28/40 , H01G4/10 , H01G13/00 , H01L27/101 , H01L28/57 , Y10T29/435
Abstract: In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening.
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公开(公告)号：US20090067213A1
公开(公告)日：2009-03-12
申请号：US11899597
申请日：2007-09-06
Applicant: Matthew Buynoski , Seungmoo Choi , Chakravarthy Gopalan , Dongxiang Liao , Christie Marrian
Inventor： Matthew Buynoski , Seungmoo Choi , Chakravarthy Gopalan , Dongxiang Liao , Christie Marrian
CPC classification number: H01L45/165 , H01L21/31683 , H01L45/04 , H01L45/08 , H01L45/10 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1608 , H01L45/1633
Abstract: In fabricating a memory device, a first electrode is provided. An alloy is formed thereon, and the alloy is oxidized to provide an oxide layer. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. Oxide is provided on the first electrode, and an implantation step in undertaken to implant material in the oxide to form a layer including oxide and implanted material having an oxygen deficiency and/or defects therein. A second electrode is then formed on the layer.
Abstract translation: 在制造存储器件时，提供第一电极。 在其上形成合金，并且将该合金氧化以提供氧化物层。 第二电极设置在氧化物层上。 在制造存储器件的另一方法中，提供第一电极。 在第一电极上提供氧化物，以及注入步骤，用于在氧化物中植入材料以形成包含氧缺陷和/或缺陷的氧化物和/或缺陷的层。 然后在该层上形成第二电极。
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3.发明申请Damascene metal-insulator-metal (MIM) device with improved scaleability 有权大马士革金属绝缘体金属（MIM）装置，具有改进的可扩展性公开(公告)号：US20080123401A1
公开(公告)日：2008-05-29
申请号：US11521204
申请日：2006-09-14
Applicant: Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael VanBuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffrey A. Shields
Inventor： Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael VanBuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffrey A. Shields
CPC classification number: H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/146 , H01L45/1633 , H01L45/1675 , H01L45/1683
Abstract: A present method of fabricating a memory device includes the steps of providing a dielectric layer;, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer.
Abstract translation: 本发明的制造存储器件的方法包括以下步骤：提供电介质层;在电介质层中提供开口，在开口中提供第一导电体，在开口中提供开关体，第一导电体和开关体 填充开口，并且在开关体上提供第二导电体。 在替代实施例中，在第一介电层上提供第二电介质层，并且开关体设置在第二电介质层的开口中。
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4.发明授权Method and system for automated generation of masks for spacer formation from a desired final wafer pattern 有权用于从期望的最终晶片图案自动生成用于间隔物形成的掩模的方法和系统公开(公告)号：US09274410B2
公开(公告)日：2016-03-01
申请号：US12701391
申请日：2010-02-05
Applicant: Wai Lo , Todd Lukanc , Christie Marrian
Inventor： Wai Lo , Todd Lukanc , Christie Marrian
Abstract: Methods and systems for generating masks for spacer formation are disclosed. As a part of a disclosed method, a predefined final wafer pattern is accessed, areas related to features in the predefined final wafer pattern are identified and a template mask is formed based on the identified areas for forming spacers on a wafer. Subsequently, a mask is formed for use in the removal of portions of the spacers to form an on wafer pattern that corresponds to the predefined final wafer pattern.
Abstract translation: 公开了用于产生用于间隔物形成的掩模的方法和系统。 作为所公开的方法的一部分，访问预定义的最终晶片图案，识别与预定的最终晶片图案中的特征相关的区域，并且基于用于在晶片上形成间隔物的所识别的区域形成模板掩模。 随后，形成用于去除间隔物的部分以形成对应于预定的最终晶片图案的晶片图案的掩模。
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5.发明授权公开(公告)号：US07706168B2
公开(公告)日：2010-04-27
申请号：US11980116
申请日：2007-10-30
Applicant: Tzu-Ning Fang , Steven Avanzino , Swaroop Kaza , Dongxiang Liao , Christie Marrian , Sameer Haddad
Inventor： Tzu-Ning Fang , Steven Avanzino , Swaroop Kaza , Dongxiang Liao , Christie Marrian , Sameer Haddad
IPC: G11C11/00
CPC classification number: G11C13/0007 , G11C2213/32 , G11C2213/34 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1633
Abstract: The present method provides annealing of a resistive memory device so as to provide that the device in its erased state has a greatly increased resistance as compared to a prior art approach. The annealing also provides that the device may be erased by application of any of a plurality of electrical potentials within an increased range of electrical potentials as compared to the prior art.
Abstract translation: 本方法提供了电阻式存储器件的退火，从而使得与现有技术方法相比，处于其擦除状态的器件具有大大增加的电阻。 退火还规定，与现有技术相比，可以在增加的电位范围内通过施加多个电位中的任何一个来擦除器件。
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Patent Agency Ranking
6.发明申请公开(公告)号：US20090109727A1
公开(公告)日：2009-04-30
申请号：US11980116
申请日：2007-10-30
Applicant: Tzu-Ning Fang , Steven Avanzino , Swaroop Kaza , Dongxiang Liao , Christie Marrian , Sameer Haddad
Inventor： Tzu-Ning Fang , Steven Avanzino , Swaroop Kaza , Dongxiang Liao , Christie Marrian , Sameer Haddad
IPC: G11C11/00
CPC classification number: G11C13/0007 , G11C2213/32 , G11C2213/34 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1633
Abstract: The present method provides annealing of a resistive memory device so as to provide that the device in its erased state has a greatly increased resistance as compared to a prior art approach. The annealing also provides that the device may be erased by application of any of a plurality of electrical potentials within an increased range of electrical potentials as compared to the prior art.
Abstract translation: 本方法提供了电阻式存储器件的退火，从而使得与现有技术方法相比，处于其擦除状态的器件具有大大增加的电阻。 退火还规定，与现有技术相比，可以在增加的电位范围内通过施加多个电位中的任何一个来擦除器件。
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公开(公告)号：US08946020B2
公开(公告)日：2015-02-03
申请号：US11899597
申请日：2007-09-06
Applicant: Matthew Buynoski , Seungmoo Choi , Chakravarthy Gopalan , Dongxiang Liao , Christie Marrian
Inventor： Matthew Buynoski , Seungmoo Choi , Chakravarthy Gopalan , Dongxiang Liao , Christie Marrian
IPC: H01L21/8242 , H01L21/316 , H01L45/00
CPC classification number: H01L45/165 , H01L21/31683 , H01L45/04 , H01L45/08 , H01L45/10 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1608 , H01L45/1633
Abstract: In fabricating a memory device, a first electrode is provided. An alloy is formed thereon, and the alloy is oxidized to provide an oxide layer. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. Oxide is provided on the first electrode, and an implantation step in undertaken to implant material in the oxide to form a layer including oxide and implanted material having an oxygen deficiency and/or defects therein. A second electrode is then formed on the layer.
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8.发明申请公开(公告)号：US20120276706A1
公开(公告)日：2012-11-01
申请号：US13529284
申请日：2012-06-21
Applicant: Suzette K. PANGRLE , Steven AVANZINO , Sameer HADDAD , Michael VANBUSKIRK , Manuj RATHOR , James XIE , Kevin SONG , Christie MARRIAN , Bryan CHOO , Fei WANG , Jeffery A. SHIELDS
Inventor： Suzette K. PANGRLE , Steven AVANZINO , Sameer HADDAD , Michael VANBUSKIRK , Manuj RATHOR , James XIE , Kevin SONG , Christie MARRIAN , Bryan CHOO , Fei WANG , Jeffery A. SHIELDS
IPC: H01L21/02
CPC classification number: H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/146 , H01L45/1633 , H01L45/1675 , H01L45/1683
Abstract: A present method of fabricating a memory device includes the steps of providing a dielectric layer;, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body Filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer.
Abstract translation: 本发明的制造存储器件的方法包括以下步骤：提供电介质层;在电介质层中提供开口，在开口中提供第一导电体，在开口中提供开关体，第一导电体和开关体 填充开口，并在开关体上设置第二导电体。 在替代实施例中，在第一介电层上提供第二电介质层，并且开关体设置在第二电介质层的开口中。
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9.发明授权Damascene metal-insulator-metal (MIM) device with improved scaleability 有权大马士革金属绝缘体金属（MIM）装置，具有改进的可扩展性公开(公告)号：US08232175B2
公开(公告)日：2012-07-31
申请号：US11521204
申请日：2006-09-14
Applicant: Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael VanBuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffrey A. Shields
Inventor： Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael VanBuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffrey A. Shields
IPC: H01L21/20
CPC classification number: H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/146 , H01L45/1633 , H01L45/1675 , H01L45/1683
Abstract: A present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer.
Abstract translation: 制造存储器件的现有方法包括以下步骤：提供电介质层，在介电层中提供开口，在开口中提供第一导电体，在开口中提供开关体，第一导电体和开关体填充物 并且在开关体上设置第二导电体。 在替代实施例中，在第一介电层上提供第二电介质层，并且开关体设置在第二电介质层的开口中。
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10.发明申请METHOD AND SYSTEM FOR AUTOMATED GENERATION OF MASKS FOR SPACER FORMATION FROM A DESIRED FINAL WAFER PATTERN 有权用于自动生成用于从预期的最终波形图形形成的掩模的方法和系统公开(公告)号：US20110195348A1
公开(公告)日：2011-08-11
申请号：US12701391
申请日：2010-02-05
Applicant: Wai Lo , Todd Lukanc , Christie Marrian
Inventor： Wai Lo , Todd Lukanc , Christie Marrian
Abstract: Methods and systems for generating masks for spacer formation are disclosed. As a part of a disclosed method, a predefined final wafer pattern is accessed, areas related to features in the predefined final wafer pattern are identified and a template mask is formed based on the identified areas for forming spacers on a wafer. Subsequently, a mask is formed for use in the removal of portions of the spacers to form an on wafer pattern that corresponds to the predefined final wafer pattern.
Abstract translation: 公开了用于产生用于间隔物形成的掩模的方法和系统。 作为所公开的方法的一部分，访问预定义的最终晶片图案，识别与预定的最终晶片图案中的特征相关的区域，并且基于用于在晶片上形成间隔物的所识别的区域形成模板掩模。 随后，形成用于去除间隔物的部分以形成对应于预定的最终晶片图案的晶片图案的掩模。
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