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1.发明授权Damascene metal-insulator-metal (MIM) device with improved scaleability 有权大马士革金属绝缘体金属（MIM）装置，具有改进的可扩展性公开(公告)号：US09343666B2
公开(公告)日：2016-05-17
申请号：US13529284
申请日：2012-06-21
Applicant: Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael Vanbuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffery A. Shields
Inventor： Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael Vanbuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffery A. Shields
CPC classification number: H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/146 , H01L45/1633 , H01L45/1675 , H01L45/1683
Abstract: A present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer.
Abstract translation: 制造存储器件的现有方法包括以下步骤：提供电介质层，在电介质层中提供开口，在开口中提供第一导电体，在开口中提供开关体，第一导电体和开关体填充物 并且在开关体上设置第二导电体。 在替代实施例中，在第一介电层上提供第二电介质层，并且开关体设置在第二电介质层的开口中。
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2.发明申请
公开(公告)号：US20120276706A1
公开(公告)日：2012-11-01
申请号：US13529284
申请日：2012-06-21
Applicant: Suzette K. PANGRLE , Steven AVANZINO , Sameer HADDAD , Michael VANBUSKIRK , Manuj RATHOR , James XIE , Kevin SONG , Christie MARRIAN , Bryan CHOO , Fei WANG , Jeffery A. SHIELDS
Inventor： Suzette K. PANGRLE , Steven AVANZINO , Sameer HADDAD , Michael VANBUSKIRK , Manuj RATHOR , James XIE , Kevin SONG , Christie MARRIAN , Bryan CHOO , Fei WANG , Jeffery A. SHIELDS
IPC: H01L21/02
CPC classification number: H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/146 , H01L45/1633 , H01L45/1675 , H01L45/1683
Abstract: A present method of fabricating a memory device includes the steps of providing a dielectric layer;, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body Filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer.
Abstract translation: 本发明的制造存储器件的方法包括以下步骤：提供电介质层;在电介质层中提供开口，在开口中提供第一导电体，在开口中提供开关体，第一导电体和开关体 填充开口，并在开关体上设置第二导电体。 在替代实施例中，在第一介电层上提供第二电介质层，并且开关体设置在第二电介质层的开口中。
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3.发明申请
公开(公告)号：US20120038051A1
公开(公告)日：2012-02-16
申请号：US13281491
申请日：2011-10-26
Applicant: Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffery A. Shields , Jusuke Ogura
Inventor： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffery A. Shields , Jusuke Ogura
IPC: H01L23/48 , H01L21/768
CPC classification number: H01L21/28518 , H01L21/743 , H01L21/76895
Abstract: A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.
Abstract translation: 掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。 硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。 在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。 然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。 凹槽里填充有抛光的填充材料。 然后去除硬掩模以形成硅化物掩埋的局部互连。
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4.发明授权Buried silicide local interconnect with sidewall spacers and method for making the same 有权埋入硅化物与侧壁间隔物的局部互连及其制造方法
公开(公告)号：US07786003B1
公开(公告)日：2010-08-31
申请号：US11136569
申请日：2005-05-25
Applicant: Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffery A. Shields , Jusuke Ogura
Inventor： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffery A. Shields , Jusuke Ogura
IPC: H01L21/4763
CPC classification number: H01L21/28518 , H01L21/743 , H01L21/76895
Abstract: A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.
Abstract translation: 掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。 硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。 在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。 然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。 凹槽里填充有抛光的填充材料。 然后去除硬掩模以形成硅化物掩埋的局部互连。
