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1004 条记录 (耗时 0.022 秒)

    Method and apparatus for improvements in chip manufacture and design
    51.
    发明授权
    Method and apparatus for improvements in chip manufacture and design 有权
    改进芯片制造和设计的方法和装置

    公开(公告)号：US07955973B2

    公开(公告)日：2011-06-07

    申请号：US12375854

    申请日：2006-08-01

    申请人： Michel Zecri

    发明人： Michel Zecri

    IPC分类号： H01L21/44 ,  H01L23/42

    CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05553 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2224/45099

    摘要： A method of securing a bond pad in to a semiconductor chip having an upper top metal surface which includes one or more holes, the method comprising the steps of forming a passivation layer over the upper metal surface, which passivation layer has holes therein substantially corresponding to the or each hole in the upper metal layer and being substantially the same size or smaller than the holes in the upper metal layer; forming the bond pad over the passivation layer; characterised in that the step of forming the bond pad comprises introducing some of the material from the bond pad into the holes in the passivation layer and upper metal layer when forming the bond pad, securing the bond pad to the passivation layer by allowing said material to flow under the surface thereof and attach thereto without attaching to the upper metal layer to thereby form a securing means.

    摘要翻译： 一种将接合焊盘固定到具有包括一个或多个孔的上顶部金属表面的半导体芯片的方法，所述方法包括以下步骤：在所述上部金属表面上形成钝化层，所述钝化层在其中基本对应于 上金属层中的每个孔或与上金属层中的孔基本相同的尺寸或更小的孔; 在所述钝化层上形成所述接合焊盘; 其特征在于，形成所述接合焊盘的步骤包括在形成所述接合焊盘时将来自所述接合焊盘的一些材料引入所述钝化层和所述上金属层中的孔中，通过允许所述材料将所述接合焊盘固定到所述钝化层 在其表面下流动并附着在其上而不附着到上金属层，从而形成固定装置。

    Semiconductor wafer, semiconductor device, and semiconductor device manufacturing method
    56.
    发明授权
    Semiconductor wafer, semiconductor device, and semiconductor device manufacturing method 失效
    半导体晶片，半导体器件和半导体器件制造方法

    公开(公告)号：US07919847B2

    公开(公告)日：2011-04-05

    申请号：US11713436

    申请日：2007-03-02

    申请人： Atsushi Ebara

    发明人： Atsushi Ebara

    IPC分类号： H01L23/48

    CPC分类号： H01L21/78 ,  H01L22/32 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05554 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19043

    摘要： A semiconductor wafer includes a plurality of chip areas, a scribe line area, a bonding pad, a probing pad, and a pad connection wiring. The plurality of chip areas are configured to be arranged in a matrix form. The scribe line area is configured to separate the plurality of chip areas from each other. The bonding pad is configured to be connected with an external terminal. The probing pad is configured to be contacted with a probe wire. The pad connection wiring is configured to electrically connect the bonding pad to the probing pad. The bonding pad and the probing pad are located at a predetermined distance from each other in each of the plurality of chip areas. The pad connection wiring has a portion located in the scribe line area.

    摘要翻译： 半导体晶片包括多个芯片区域，划线区域，焊盘，探测焊盘和焊盘连接布线。 多个芯片区域被配置为以矩阵形式布置。 划线部分被配置为将多个芯片区域彼此分开。 接合焊盘被配置为与外部端子连接。 探测垫被配置成与探针线接触。 焊盘连接布线被配置为将焊盘电连接到探测板。 接合焊盘和探测垫位于多个芯片区域中的每一个中彼此预定的距离。 焊盘连接布线具有位于划线区域中的部分。

    Semiconductor device
    57.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07898035B2

    公开(公告)日：2011-03-01

    申请号：US12315635

    申请日：2008-12-04

    申请人： Hiroaki Takasu ,  Sukehiro Yamamoto

    发明人： Hiroaki Takasu ,  Sukehiro Yamamoto

    IPC分类号： H01L23/62

    CPC分类号： H01L21/823475 ,  H01L21/823418 ,  H01L24/05 ,  H01L27/0266 ,  H01L29/4238 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05556 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

    摘要： A semiconductor device has a silicon substrate, an external connection terminal disposed on the silicon substrate, an internal circuit region disposed on the silicon substrate, an NMOS transistor for electrostatic discharge protection provided between the external connection terminal and the internal circuit region, and a wiring connecting together the external connection terminal and the NMOS transistor and connecting together the NMOS transistor and the internal circuit region. The NMOS transistor has a drain region and a gate electrode whose potential is fixed to a ground potential. The external connection terminal is smaller than the drain region and is formed above the drain region.

    摘要翻译： 半导体器件具有硅衬底，设置在硅衬底上的外部连接端子，设置在硅衬底上的内部电路区域，设置在外部连接端子和内部电路区域之间的用于静电放电保护的NMOS晶体管和布线 将外部连接端子和NMOS晶体管连接在一起并将NMOS晶体管和内部电路区域连接在一起。 NMOS晶体管具有漏极区域和电位固定在接地电位的栅极电极。 外部连接端子小于漏极区域，并形成在漏极区域的上方。