公开(公告)号：US07667280B2

公开(公告)日：2010-02-23

申请号：US12030294

申请日：2008-02-13

申请人： Hiroaki Takasu ,  Naoto Inoue ,  Sukehiro Yamamoto

发明人： Hiroaki Takasu ,  Naoto Inoue ,  Sukehiro Yamamoto

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L27/0921

摘要： Provided is a semiconductor device having a trench isolation structure and a high power supply voltage circuit section including at least a well region and a MOS transistor formed therein. The high power supply voltage circuit section includes a carrier capture region for preventing latch-up in a vicinity of an end portion of the well region, and a depth of the carrier capture region is larger than a depth of the trench isolation region. The carrier capture region in the high power supply voltage circuit section is formed of a diffusion layer which is the same as that of a source or a drain region of the MOS transistor formed in the high power supply voltage circuit section.

摘要翻译： 提供了具有沟槽隔离结构的半导体器件和至少包括形成在其中的阱区和MOS晶体管的高电源电压电路部分。 高电源电压电路部分包括用于防止在阱区域的端部附近闩锁的载体捕获区域，并且载体捕获区域的深度大于沟槽隔离区域的深度。 高电源电压电路部中的载流子俘获区域由形成在高电源电压电路部中的MOS晶体管的源极或漏极区域的扩散层构成。

公开(公告)号：US20090050968A1

公开(公告)日：2009-02-26

申请号：US12191693

申请日：2008-08-14

申请人： Hiroaki Takasu ,  Takayuki Takashina ,  Sukehiro Yamamoto

发明人： Hiroaki Takasu ,  Takayuki Takashina ,  Sukehiro Yamamoto

IPC分类号： H01L23/62

CPC分类号： H01L27/0266 ,  H01L29/0696 ,  H01L29/41758 ,  H01L29/78

摘要： Provided is a semiconductor device including an n-type metal oxide semiconductor transistor for electrostatic discharge protection including drain regions connected with a first metal interconnect and source regions connected with another first metal interconnect alternately placed with each other, and gate electrodes each placed between each of the drain regions and each of the source regions, in which: at least one of the first metal interconnect and the other first metal interconnect being connected to a plurality of layers of metal interconnects other than the first metal interconnect; and the source regions include via-holes for electrically connecting the other first metal interconnect and the plurality of layers of metal interconnects other than the first metal interconnect, a greater number of the via-holes is formed as a distance of an interconnect connected to the NMOS transistor for ESD protection becomes larger.

摘要翻译： 提供一种半导体器件，其包括用于静电放电保护的n型金属氧化物半导体晶体管，其包括与第一金属互连连接的漏极区域和与彼此交替放置的另一个第一金属互连件连接的源极区域，以及分别位于 漏极区域和每个源极区域，其中：第一金属互连和另一个第一金属互连中的至少一个连接到除了第一金属互连之外的多个金属互连层; 并且源极区域包括用于电连接另一个第一金属互连件和除了第一金属互连件之外的多个金属互连层的通孔，更多的通孔形成为连接到第一金属互连件的互连件的距离 用于ESD保护的NMOS晶体管变大。

公开(公告)号：US06800923B1

公开(公告)日：2004-10-05

申请号：US10422909

申请日：2003-04-25

申请人： Sukehiro Yamamoto

发明人： Sukehiro Yamamoto

IPC分类号： H01L2900

CPC分类号： H01L23/5223 ,  H01L21/76802 ,  H01L23/5226 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

摘要： A mixed-signal integrated circuit includes a metal-insulator-metal or polysilicon-insulator-polysilicon capacitor. The electrical path from one electrode of the capacitor passes through a first interconnecting line, then through multiple via holes to a second interconnecting line. During the fabrication process, the capacitor is first charged during a plasma deposition process used to deposit an interlayer dielectric film between the first and second interconnecting lines, then abruptly discharged during a plasma etching process that forms the via holes. The discharge does not damage the floors of the via holes, however, because each of the multiple via holes carries only part of the discharge current.

摘要翻译： 混合信号集成电路包括金属 - 绝缘体金属或多晶硅 - 绝缘体 - 多晶硅电容器。 电容器的一个电极的电路通过第一互连线，然后通过多个通孔到第二互连线。 在制造过程中，电容器首先在等离子体沉积工艺期间被充电，用于在第一和第二互连线之间沉积层间绝缘膜，然后在形成通孔的等离子体蚀刻工艺期间突然放电。 放电不会损坏通孔的地板，但是，因为多个通孔中的每一个仅承载部分放电电流。

公开(公告)号：US20120199977A1

公开(公告)日：2012-08-09

申请号：US13362678

申请日：2012-01-31

申请人： Sukehiro YAMAMOTO

发明人： Sukehiro YAMAMOTO

IPC分类号： H01L23/485

CPC分类号： H01L24/05 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05624 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074

摘要： To prevent generation of cracks in an insulating film provided under a bonding pad, a semiconductor device includes a three-layered bonding pad, and the three-layered bonding pad includes a first metal film, a second metal film, and a third metal film, in which the second metal film has a Young's modulus higher than a Young's modulus of the first metal film and a Young's modulus of the third metal film.

摘要翻译： 为了防止在焊盘上设置的绝缘膜中产生裂纹，半导体器件包括三层接合焊盘，并且三层接合焊盘包括第一金属膜，第二金属膜和第三金属膜， 其中第二金属膜的杨氏模量高于第一金属膜的杨氏模量和第三金属膜的杨氏模量。

公开(公告)号：US20110233677A1

公开(公告)日：2011-09-29

申请号：US13070170

申请日：2011-03-23

申请人： Sukehiro Yamamoto

发明人： Sukehiro Yamamoto

IPC分类号： H01L27/088

CPC分类号： H01L27/027 ,  H01L29/41758 ,  H01L29/4238

摘要： Provided is a semiconductor device having an ESD protection MOS transistor including a plurality of transistors combined together, in which a plurality of drain regions and a plurality of source regions disposed alternately and a gate electrode disposed between each pair of adjacent regions constituted of one of the plurality of drain regions and one of the plurality of source regions, in which a distance between a salicide metal region, which is formed on each of the plurality of drain regions, and the gate electrode is determined according to contact holes in the plurality of drain regions and a distance of the contact holes from substrate contacts.

摘要翻译： 提供一种具有ESD保护MOS晶体管的半导体器件，该ESD保护MOS晶体管包括组合在一起的多个晶体管，其中交替设置多个漏极区域和多个源极区域以及设置在由一个相邻区域中的一个构成的每对相邻区域之间的栅电极 多个漏极区域和多个源极区域中的一个，其中形成在多个漏极区域中的每一个上的自对准金属区域与栅电极之间的距离根据多个漏极中的接触孔来确定 区域和接触孔与基板触点的距离。

公开(公告)号：US20090121223A1

公开(公告)日：2009-05-14

申请号：US12354423

申请日：2009-01-15

申请人： Hiroaki Takasu ,  Sukehiro Yamamoto

发明人： Hiroaki Takasu ,  Sukehiro Yamamoto

IPC分类号： H01L29/10

CPC分类号： H01L23/544 ,  G01R31/2884 ,  G01R31/2887 ,  H01L2223/5446 ,  H01L2223/5448 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor device, in which: patterns for detecting displacement at probing are formed of a plurality of minute conductors formed below a protective film; each of the plurality of minute conductors formed below the protective film is electrically insulated and formed to be smaller than a bottom surface of a tip of a probing needle used for carrying out an electrical measurement of IC chips; and the patterns for detecting displacement at probing are provided in a pair for each of the IC chips.

摘要翻译： 提供一种半导体器件，其中：用于检测探测位移的图案由形成在保护膜下面的多个微小导体形成; 形成在保护膜下方的多个微导体中的每一个电绝缘并形成为小于用于执行IC芯片的电测量的探针的尖端的底表面; 并且针对每个IC芯片成对地设置用于检测探测位移的图案。

公开(公告)号：US20080191308A1

公开(公告)日：2008-08-14

申请号：US12030294

申请日：2008-02-13

申请人： Hiroaki Takasu ,  Naoto Inoue ,  Sukehiro Yamamoto

发明人： Hiroaki Takasu ,  Naoto Inoue ,  Sukehiro Yamamoto

IPC分类号： H01L27/06

CPC分类号： H01L27/0921

摘要： Provided is a semiconductor device having a trench isolation structure and a high power supply voltage circuit section including at least a well region and a MOS transistor formed therein. The high power supply voltage circuit section includes a carrier capture region for preventing latch-up in a vicinity of an end portion of the well region, and a depth of the carrier capture region is larger than a depth of the trench isolation region. The carrier capture region in the high power supply voltage circuit section is formed of a diffusion layer which is the same as that of a source or a drain region of the MOS transistor formed in the high power supply voltage circuit section.

摘要翻译： 提供了具有沟槽隔离结构的半导体器件和至少包括形成在其中的阱区和MOS晶体管的高电源电压电路部分。 高电源电压电路部分包括用于防止在阱区域的端部附近闩锁的载体捕获区域，并且载体捕获区域的深度大于沟槽隔离区域的深度。 高电源电压电路部中的载流子俘获区域由形成在高电源电压电路部中的MOS晶体管的源极或漏极区域的扩散层构成。

公开(公告)号：US20080001146A1

公开(公告)日：2008-01-03

申请号：US11818123

申请日：2007-06-13

申请人： Hiroaki Takasu ,  Sukehiro Yamamoto

发明人： Hiroaki Takasu ,  Sukehiro Yamamoto

IPC分类号： H01L23/58

CPC分类号： H01L23/544 ,  G01R31/2884 ,  G01R31/2887 ,  H01L2223/5446 ,  H01L2223/5448 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor device, in which: patterns for detecting displacement at probing are formed of a plurality of minute conductors formed below a protective film; each of the plurality of minute conductors formed below the protective film is electrically insulated and formed to be smaller than a bottom surface of a tip of a probing needle used for carrying out an electrical measurement of IC chips; and the patterns for detecting displacement at probing are provided in a pair for each of the IC chips.

摘要翻译： 提供一种半导体器件，其中：用于检测探测位移的图案由形成在保护膜下面的多个微小导体形成; 形成在保护膜下方的多个微导体中的每一个电绝缘并形成为小于用于执行IC芯片的电测量的探针的尖端的底表面; 并且针对每个IC芯片成对地设置用于检测探测位移的图案。

公开(公告)号：US07109088B2

公开(公告)日：2006-09-19

申请号：US10923744

申请日：2004-08-24

申请人： Sukehiro Yamamoto

发明人： Sukehiro Yamamoto

IPC分类号： H01L21/20

CPC分类号： H01L23/5223 ,  H01L21/76802 ,  H01L23/5226 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

摘要： A mixed-signal integrated circuit includes a metal-insulator-metal or polysilicon-insulator-polysilicon capacitor. The electrical path from one electrode of the capacitor passes through a first interconnecting line, then through multiple via holes to a second interconnecting line. During the fabrication process, the capacitor is first charged during a plasma deposition process used to deposit an interlayer dielectric film between the first and second interconnecting lines, then abruptly discharged during a plasma etching process that forms the via holes. The discharge does not damage the floors of the via holes, however, because each of the multiple via holes carries only part of the discharge current.

摘要翻译： 混合信号集成电路包括金属 - 绝缘体金属或多晶硅 - 绝缘体 - 多晶硅电容器。 电容器的一个电极的电路通过第一互连线，然后通过多个通孔到第二互连线。 在制造过程中，电容器首先在等离子体沉积工艺期间被充电，用于在第一和第二互连线之间沉积层间绝缘膜，然后在形成通孔的等离子体蚀刻工艺期间突然放电。 放电不会损坏通孔的地板，但是，因为多个通孔中的每一个仅承载部分放电电流。

公开(公告)号：US07015143B2

公开(公告)日：2006-03-21

申请号：US10309167

申请日：2002-12-04

申请人： Sukehiro Yamamoto

发明人： Sukehiro Yamamoto

IPC分类号： H01L21/302

CPC分类号： H01L21/76801 ,  H01L21/76831 ,  H01L21/76837

摘要： A method for forming a structure including multiple wire-layers, the method including providing a plurality of first wires (in a layer) on an underlying layer; providing a liner insulating film on the underlying layer so as to coat the first wires and have concave portions respectively between the mutually adjacent first wires; providing a buried insulating film in the concave portions and on the liner insulating film; providing a cap insulating film so as to coat the buried insulating film; and providing a second wire layer on or above the cap insulating film. The buried insulating film is made of an insulating material having a dielectric constant, which is lower than that of the liner insulating film and the cap insulating film.

摘要翻译： 一种用于形成包括多个线层的结构的方法，所述方法包括在下层上提供多个第一布线（在一层中）; 在下层上设置衬垫绝缘膜，以便涂覆第一布线，并在相互相邻的第一布线之间分别具有凹形部分; 在凹部和衬垫绝缘膜上设置掩埋绝缘膜; 提供帽绝缘膜以覆盖所述埋入绝缘膜; 以及在帽绝缘膜上或上方提供第二导线层。 掩埋绝缘膜由介电常数低于衬垫绝缘膜和帽绝缘膜的绝缘材料制成。