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公开(公告)号：US07667280B2
公开(公告)日：2010-02-23
申请号：US12030294
申请日：2008-02-13
申请人： Hiroaki Takasu , Naoto Inoue , Sukehiro Yamamoto
发明人： Hiroaki Takasu , Naoto Inoue , Sukehiro Yamamoto
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L27/0921
摘要： Provided is a semiconductor device having a trench isolation structure and a high power supply voltage circuit section including at least a well region and a MOS transistor formed therein. The high power supply voltage circuit section includes a carrier capture region for preventing latch-up in a vicinity of an end portion of the well region, and a depth of the carrier capture region is larger than a depth of the trench isolation region. The carrier capture region in the high power supply voltage circuit section is formed of a diffusion layer which is the same as that of a source or a drain region of the MOS transistor formed in the high power supply voltage circuit section.
摘要翻译： 提供了具有沟槽隔离结构的半导体器件和至少包括形成在其中的阱区和MOS晶体管的高电源电压电路部分。 高电源电压电路部分包括用于防止在阱区域的端部附近闩锁的载体捕获区域，并且载体捕获区域的深度大于沟槽隔离区域的深度。 高电源电压电路部中的载流子俘获区域由形成在高电源电压电路部中的MOS晶体管的源极或漏极区域的扩散层构成。
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公开(公告)号：US20090050968A1
公开(公告)日：2009-02-26
申请号：US12191693
申请日：2008-08-14
IPC分类号： H01L23/62
CPC分类号： H01L27/0266 , H01L29/0696 , H01L29/41758 , H01L29/78
摘要： Provided is a semiconductor device including an n-type metal oxide semiconductor transistor for electrostatic discharge protection including drain regions connected with a first metal interconnect and source regions connected with another first metal interconnect alternately placed with each other, and gate electrodes each placed between each of the drain regions and each of the source regions, in which: at least one of the first metal interconnect and the other first metal interconnect being connected to a plurality of layers of metal interconnects other than the first metal interconnect; and the source regions include via-holes for electrically connecting the other first metal interconnect and the plurality of layers of metal interconnects other than the first metal interconnect, a greater number of the via-holes is formed as a distance of an interconnect connected to the NMOS transistor for ESD protection becomes larger.
摘要翻译： 提供一种半导体器件，其包括用于静电放电保护的n型金属氧化物半导体晶体管，其包括与第一金属互连连接的漏极区域和与彼此交替放置的另一个第一金属互连件连接的源极区域，以及分别位于 漏极区域和每个源极区域，其中：第一金属互连和另一个第一金属互连中的至少一个连接到除了第一金属互连之外的多个金属互连层; 并且源极区域包括用于电连接另一个第一金属互连件和除了第一金属互连件之外的多个金属互连层的通孔，更多的通孔形成为连接到第一金属互连件的互连件的距离 用于ESD保护的NMOS晶体管变大。
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公开(公告)号：US20090121223A1
公开(公告)日：2009-05-14
申请号：US12354423
申请日：2009-01-15
申请人： Hiroaki Takasu , Sukehiro Yamamoto
发明人： Hiroaki Takasu , Sukehiro Yamamoto
IPC分类号： H01L29/10
CPC分类号： H01L23/544 , G01R31/2884 , G01R31/2887 , H01L2223/5446 , H01L2223/5448 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device, in which: patterns for detecting displacement at probing are formed of a plurality of minute conductors formed below a protective film; each of the plurality of minute conductors formed below the protective film is electrically insulated and formed to be smaller than a bottom surface of a tip of a probing needle used for carrying out an electrical measurement of IC chips; and the patterns for detecting displacement at probing are provided in a pair for each of the IC chips.
摘要翻译： 提供一种半导体器件，其中：用于检测探测位移的图案由形成在保护膜下面的多个微小导体形成; 形成在保护膜下方的多个微导体中的每一个电绝缘并形成为小于用于执行IC芯片的电测量的探针的尖端的底表面; 并且针对每个IC芯片成对地设置用于检测探测位移的图案。
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公开(公告)号：US20080191308A1
公开(公告)日：2008-08-14
申请号：US12030294
申请日：2008-02-13
申请人： Hiroaki Takasu , Naoto Inoue , Sukehiro Yamamoto
发明人： Hiroaki Takasu , Naoto Inoue , Sukehiro Yamamoto
IPC分类号： H01L27/06
CPC分类号： H01L27/0921
摘要： Provided is a semiconductor device having a trench isolation structure and a high power supply voltage circuit section including at least a well region and a MOS transistor formed therein. The high power supply voltage circuit section includes a carrier capture region for preventing latch-up in a vicinity of an end portion of the well region, and a depth of the carrier capture region is larger than a depth of the trench isolation region. The carrier capture region in the high power supply voltage circuit section is formed of a diffusion layer which is the same as that of a source or a drain region of the MOS transistor formed in the high power supply voltage circuit section.
摘要翻译： 提供了具有沟槽隔离结构的半导体器件和至少包括形成在其中的阱区和MOS晶体管的高电源电压电路部分。 高电源电压电路部分包括用于防止在阱区域的端部附近闩锁的载体捕获区域，并且载体捕获区域的深度大于沟槽隔离区域的深度。 高电源电压电路部中的载流子俘获区域由形成在高电源电压电路部中的MOS晶体管的源极或漏极区域的扩散层构成。
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公开(公告)号：US20080001146A1
公开(公告)日：2008-01-03
申请号：US11818123
申请日：2007-06-13
申请人： Hiroaki Takasu , Sukehiro Yamamoto
发明人： Hiroaki Takasu , Sukehiro Yamamoto
IPC分类号： H01L23/58
CPC分类号： H01L23/544 , G01R31/2884 , G01R31/2887 , H01L2223/5446 , H01L2223/5448 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device, in which: patterns for detecting displacement at probing are formed of a plurality of minute conductors formed below a protective film; each of the plurality of minute conductors formed below the protective film is electrically insulated and formed to be smaller than a bottom surface of a tip of a probing needle used for carrying out an electrical measurement of IC chips; and the patterns for detecting displacement at probing are provided in a pair for each of the IC chips.
摘要翻译： 提供一种半导体器件，其中：用于检测探测位移的图案由形成在保护膜下面的多个微小导体形成; 形成在保护膜下方的多个微导体中的每一个电绝缘并形成为小于用于执行IC芯片的电测量的探针的尖端的底表面; 并且针对每个IC芯片成对地设置用于检测探测位移的图案。
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公开(公告)号：US07898035B2
公开(公告)日：2011-03-01
申请号：US12315635
申请日：2008-12-04
申请人： Hiroaki Takasu , Sukehiro Yamamoto
发明人： Hiroaki Takasu , Sukehiro Yamamoto
IPC分类号： H01L23/62
CPC分类号： H01L21/823475 , H01L21/823418 , H01L24/05 , H01L27/0266 , H01L29/4238 , H01L2224/02166 , H01L2224/05093 , H01L2224/05556 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： A semiconductor device has a silicon substrate, an external connection terminal disposed on the silicon substrate, an internal circuit region disposed on the silicon substrate, an NMOS transistor for electrostatic discharge protection provided between the external connection terminal and the internal circuit region, and a wiring connecting together the external connection terminal and the NMOS transistor and connecting together the NMOS transistor and the internal circuit region. The NMOS transistor has a drain region and a gate electrode whose potential is fixed to a ground potential. The external connection terminal is smaller than the drain region and is formed above the drain region.
摘要翻译： 半导体器件具有硅衬底，设置在硅衬底上的外部连接端子，设置在硅衬底上的内部电路区域，设置在外部连接端子和内部电路区域之间的用于静电放电保护的NMOS晶体管和布线 将外部连接端子和NMOS晶体管连接在一起并将NMOS晶体管和内部电路区域连接在一起。 NMOS晶体管具有漏极区域和电位固定在接地电位的栅极电极。 外部连接端子小于漏极区域，并形成在漏极区域的上方。
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公开(公告)号：US07804313B2
公开(公告)日：2010-09-28
申请号：US12354423
申请日：2009-01-15
申请人： Hiroaki Takasu , Sukehiro Yamamoto
发明人： Hiroaki Takasu , Sukehiro Yamamoto
CPC分类号： H01L23/544 , G01R31/2884 , G01R31/2887 , H01L2223/5446 , H01L2223/5448 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device, in which: patterns for detecting displacement at probing are formed of a plurality of minute conductors formed below a protective film; each of the plurality of minute conductors formed below the protective film is electrically insulated and formed to be smaller than a bottom surface of a tip of a probing needle used for carrying out an electrical measurement of IC chips; and the patterns for detecting displacement at probing are provided in a pair for each of the IC chips.
摘要翻译： 提供一种半导体器件，其中：用于检测探测位移的图案由形成在保护膜下面的多个微小导体形成; 形成在保护膜下方的多个微导体中的每一个电绝缘并形成为小于用于执行IC芯片的电测量的探针的尖端的底表面; 并且针对每个IC芯片成对地设置用于检测探测位移的图案。
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公开(公告)号：US07750409B2
公开(公告)日：2010-07-06
申请号：US12191693
申请日：2008-08-14
IPC分类号： H01L23/62
CPC分类号： H01L27/0266 , H01L29/0696 , H01L29/41758 , H01L29/78
摘要： Provided is a semiconductor device including an n-type metal oxide semiconductor transistor for electrostatic discharge protection including drain regions connected with a first metal interconnect and source regions connected with another first metal interconnect alternately placed with each other, and gate electrodes each placed between each of the drain regions and each of the source regions, in which: at least one of the first metal interconnect and the other first metal interconnect being connected to a plurality of layers of metal interconnects other than the first metal interconnect; and the source regions include via-holes for electrically connecting the other first metal interconnect and the plurality of layers of metal interconnects other than the first metal interconnect, a greater number of the via-holes is formed as a distance of an interconnect connected to the NMOS transistor for ESD protection becomes larger.
摘要翻译： 提供一种半导体器件，其包括用于静电放电保护的n型金属氧化物半导体晶体管，其包括与第一金属互连连接的漏极区域和与彼此交替放置的另一个第一金属互连件连接的源极区域，以及分别位于 漏极区域和每个源极区域，其中：第一金属互连和另一个第一金属互连中的至少一个连接到除了第一金属互连之外的多个金属互连层; 并且源极区域包括用于电连接另一个第一金属互连件和除了第一金属互连件之外的多个金属互连层的通孔，更多的通孔形成为连接到第一金属互连件的互连件的距离 用于ESD保护的NMOS晶体管变大。
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公开(公告)号：US20090152633A1
公开(公告)日：2009-06-18
申请号：US12315635
申请日：2008-12-04
申请人： Hiroaki Takasu , Sukehiro Yamamoto
发明人： Hiroaki Takasu , Sukehiro Yamamoto
IPC分类号： H01L29/78
CPC分类号： H01L21/823475 , H01L21/823418 , H01L24/05 , H01L27/0266 , H01L29/4238 , H01L2224/02166 , H01L2224/05093 , H01L2224/05556 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： In a semiconductor device including, between an external connection terminal and an internal circuit region, an NMOS transistor for ESD protection having a gate potential fixed to a ground potential, the external connection terminal is formed above a drain region of the NMOS transistor for ESD protection, and the drain region is surrounded by a source region through a channel region. Further, the drain region has a shape with rounded corners in plan view.
摘要翻译： 在包括在外部连接端子和内部电路区域之间的半导体器件中，具有固定在接地电位上的栅极电位的用于ESD保护的NMOS晶体管，外部连接端子形成在用于ESD保护的NMOS晶体管的漏极区域之上 并且漏极区域被源区域通过沟道区域包围。 此外，漏极区域在平面图中具有圆角。
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公开(公告)号：US07535240B2
公开(公告)日：2009-05-19
申请号：US11818123
申请日：2007-06-13
申请人： Hiroaki Takasu , Sukehiro Yamamoto
发明人： Hiroaki Takasu , Sukehiro Yamamoto
CPC分类号： H01L23/544 , G01R31/2884 , G01R31/2887 , H01L2223/5446 , H01L2223/5448 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device, in which: patterns for detecting displacement at probing are formed of a plurality of minute conductors formed below a protective film; each of the plurality of minute conductors formed below the protective film is electrically insulated and formed to be smaller than a bottom surface of a tip of a probing needle used for carrying out an electrical measurement of IC chips; and the patterns for detecting displacement at probing are provided in a pair for each of the IC chips.
摘要翻译： 提供一种半导体器件，其中：用于检测探测位移的图案由形成在保护膜下面的多个微小导体形成; 形成在保护膜下方的多个微导体中的每一个电绝缘并形成为小于用于执行IC芯片的电测量的探针的尖端的底表面; 并且针对每个IC芯片成对地设置用于检测探测位移的图案。
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