公开(公告)号：US20240206193A1

公开(公告)日：2024-06-20

申请号：US18151742

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chuei-Tang WANG ,  Tso-Jung CHANG ,  Wen-Shiang LIAO ,  Jeng-Shien HSIEH ,  Chih-Peng LIN ,  Shih-Ping LIN ,  Chieh-Yen CHEN ,  Chen-Hua YU

IPC: H10B80/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H10B80/00 ,  H01L23/3128 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2924/15311

Abstract: A package structure and a formation method are provided. The method includes bonding a first memory-containing chip structure to a second memory-containing chip structure through dielectric-to-dielectric bonding and metal-to-metal bonding. The method also includes bonding a logic control chip structure to the second memory-containing chip structure through dielectric-to-dielectric bonding and metal-to-metal bonding. The logic control chip structure is formed using a more advanced technology node than the second memory-containing chip structure.

公开(公告)号：US20240128147A1

公开(公告)日：2024-04-18

申请号：US18099348

申请日：2023-01-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Sey-Ping SUN ,  Chen-Hua YU ,  Shih Wei LIANG

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/373 ,  H10B80/00

CPC classification number: H01L23/3675 ,  H01L23/3738 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H10B80/00 ,  H01L24/80 ,  H01L2224/03452 ,  H01L2224/05186 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05638 ,  H01L2224/05686 ,  H01L2224/08145 ,  H01L2224/08221 ,  H01L2224/09181 ,  H01L2224/09505 ,  H01L2224/09519 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80438 ,  H01L2224/80486 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/01014 ,  H01L2924/05032

Abstract: A semiconductor device is provided. The semiconductor includes a supporting silicon layer and a memory module. The memory module and the supporting silicon layer are bonded via a bonding structure. The bonding structure includes at least one bonding film whose thickness is less than 200 Å.

公开(公告)号：US20240047365A1

公开(公告)日：2024-02-08

申请号：US18150539

申请日：2023-01-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chuei-Tang WANG ,  Tso-Jung CHANG ,  Jeng-Shien HSIEH ,  Shih-Ping LIN ,  Chieh-Yen CHEN ,  Chen-Hua YU

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48

CPC classification number: H01L23/5386 ,  H01L24/13 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0652 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/5383 ,  H01L2224/13023 ,  H01L2224/08235 ,  H01L2224/08146 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/182

Abstract: A package structure and a formation method are provided. The method includes disposing a first chip structure and a second chip structure over a carrier substrate. The method also includes forming an interconnection structure directly over and contacting the first chip structure and the second chip structure. The interconnection structure has multiple dielectric layers and multiple conductive features. One of the conductive features extends across a first edge of the first chip structure and a second edge of the second chip structure and is electrically connecting the first chip structure and the second chip structure. The method further includes directly bonding a third chip structure to the interconnection structure through dielectric-to-dielectric bonding and metal-to-metal bonding.

公开(公告)号：US20210375724A1

公开(公告)日：2021-12-02

申请号：US17402920

申请日：2021-08-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tung-Liang SHAO ,  Wen-Lin SHIH ,  Su-Chun YANG ,  Chih-Hang TUNG ,  Chen-Hua YU

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L25/00

Abstract: A package structure is provided. The package structure includes a first interconnect structure formed over a first substrate. The package structure also includes a second interconnect structure formed below a second substrate. The package structure further includes a bonding structure between the first interconnect structure and the second interconnect structure. In addition, the bonding structure includes a first intermetallic compound (IMC) and a second intermetallic compound (IMC). The bonding structure also includes an underfill layer surrounding the bonding structure. A width of the first IMC is greater than a width of the second IMC, and the underfill layer covers a sidewall of the first IMC and a sidewall of the second IMC.

公开(公告)号：US20190067107A1

公开(公告)日：2019-02-28

申请号：US16168306

申请日：2018-10-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chen-Hua YU ,  Cheng-Hung CHANG ,  Ebin LIAO ,  Chia-Lin YU ,  Hsiang-Yi WANG ,  Chun Hua CHANG ,  Li-Hsien HUANG ,  Darryl KUO ,  Tsang-Jiuh WU ,  Wen-Chih CHIOU

IPC: H01L21/768 ,  H01L23/48 ,  H01L21/3105 ,  H01L23/498 ,  H01L21/321 ,  H01L21/306 ,  H01L21/02

Abstract: A method of making a semiconductor component includes etching a substrate to define an opening. The method further includes depositing a first dielectric liner in the opening, wherein the first dielectric liner has a first stress. The method further includes depositing a second dielectric liner over the first dielectric liner, wherein the second dielectric liner has a second stress, and a direction of the first stress is opposite a direction of the second stress. The method further includes depositing a conductive material over the second dielectric liner.

公开(公告)号：US20180108632A1

公开(公告)日：2018-04-19

申请号：US15837403

申请日：2017-12-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Su-Chun YANG ,  Yi-Li HSIAO ,  Chih-Hang TUNG ,  Chen-Hua YU

IPC: H01L23/00 ,  B23K1/00

CPC classification number: H01L24/11 ,  B23K1/0016 ,  H01L21/78 ,  H01L24/13 ,  H01L24/16 ,  H01L24/742 ,  H01L24/75 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/1183 ,  H01L2224/1184 ,  H01L2224/11848 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16506 ,  H01L2224/16507 ,  H01L2224/75252 ,  H01L2224/75317 ,  H01L2224/75501 ,  H01L2224/75502 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/75843 ,  H01L2224/7598 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/8193 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2224/81 ,  H01L2924/00

Abstract: A wafer-level pulling method includes securing a top holder to a plurality of chips. The method further includes securing a bottom holder to a wafer, wherein the plurality of chips are bonded to the wafer by a plurality of solder bumps. The method further includes softening the plurality of solder bumps. The method further includes stretching the plurality of softened solder bumps, wherein stretching the plurality of softened solder bumps comprises leveling the plurality of chips using a plurality of levelling devices separated from the plurality of chips, and a first levelling device of the plurality of levelling devices has a different structure from a second levelling device of the plurality of levelling devices.

公开(公告)号：US20160104940A1

公开(公告)日：2016-04-14

申请号：US14510796

申请日：2014-10-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chuei-Tang WANG ,  Jeng-Shieh HSIEH ,  Chung-Hao TSAI ,  Monsen LIU ,  Chen-Hua YU

IPC: H01Q19/10 ,  H01Q19/185 ,  H01Q19/00

CPC classification number: H01Q21/065 ,  H01L23/66 ,  H01L24/20 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01Q1/2283 ,  H01Q19/005 ,  H01Q19/10 ,  H01Q19/185

Abstract: An integrated fan out (InFO) antenna includes a reflector on a surface of a substrate; and a package. The package includes a redistribution layer (RDL) arranged to form an antenna ground, and a patch antenna over the RDL, wherein the RDL is between the patch antenna and the reflector. The InFO antenna further includes a plurality of connecting elements bonding the package to the reflector. Each connecting element of the plurality of connecting elements is located inside an outer perimeter of the reflector. The InFO antenna is configured to output a signal having a wavelength.

Abstract translation: 集成的风扇输出（InFO）天线包括在基板的表面上的反射器; 和一个包。 该封装包括布置成形成天线接地的再分配层（RDL）和RDL上的贴片天线，其中RDL位于贴片天线和反射器之间。 InFO天线还包括将封装结合到反射器的多个连接元件。 多个连接元件的每个连接元件位于反射器的外周边内。 InFO天线被配置为输出具有波长的信号。

公开(公告)号：US20150228604A1

公开(公告)日：2015-08-13

申请号：US14690581

申请日：2015-04-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Cheng-Lin HUANG ,  I-Ting CHEN ,  Ying Ching SHIH ,  Po-Hao TSAI ,  Szu Wei LU ,  Jing-Cheng LIN ,  Shin-Puu JENG ,  Chen-Hua YU

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0346 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/1161 ,  H01L2224/11622 ,  H01L2224/13011 ,  H01L2224/13014 ,  H01L2224/13078 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/1405 ,  H01L2224/14051 ,  H01L2224/145 ,  H01L2224/16238 ,  H01L2224/17107 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/81897 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01083 ,  H01L2924/01053 ,  H01L2924/01079 ,  H01L2924/01051 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate having a major surface and conductive bumps distributed over the major surface of the substrate. Each conductive bump of a first subset of the conductive bumps comprises a regular body and a second subset of the conductive bumps comprises a group of separate conductive bumps uniformly distributed around a periphery of a central opening.

Abstract translation: 半导体器件包括具有主表面的衬底和分布在衬底的主表面上的导电凸块。 导电凸块的第一子集的每个导电凸块包括规则体，并且导电凸块的第二子集包括均匀地分布在中心开口的周边上的一组单独的导电凸块。

公开(公告)号：US20140327464A1

公开(公告)日：2014-11-06

申请号：US14331791

申请日：2014-07-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Cheng WU ,  Hsien-Pin HU ,  Shang-Yun HOU ,  Shin-Puu JENG ,  Chen-Hua YU ,  Chao-Hsiang YANG

IPC: G01R31/28

CPC classification number: G01R31/2896 ,  G01R1/0416 ,  G01R31/2601 ,  G01R31/2884 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L22/32 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02377 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/0614 ,  H01L2224/0616 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16238 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014

Abstract: A test structure including an array of microbumps electrically connecting a chip and a substrate, wherein a width of each microbump of the array of microbumps is equal to or less than about 50 microns (μm). The test structure further includes an interconnect structure connected to the array of microbumps. The test structure further includes an array of test pads around a periphery of the array of microbumps, wherein a test pad of the array of test pads is connected to a corresponding microbump of the array of microbumps through the interconnect structure. A width of the test pad is greater than a width of the corresponding microbump, and the test pad is adapted to be covered after circuit probing by a passivation material to prevent particle and corrosion issues.

Abstract translation: 一种测试结构，其包括将芯片和基板电连接的微型阵列阵列，其中微胶片阵列的每个微型块的宽度等于或小于约50微米（μm）。 测试结构还包括连接到微丸阵列的互连结构。 该测试结构进一步包括围绕微胶片阵列周边的测试焊盘的阵列，其中测试焊盘阵列的测试焊盘通过互连结构连接到微胶片阵列的对应微型块。 测试垫的宽度大于对应的微型块的宽度，并且测试垫适于在通过钝化材料的电路探测之后被覆盖以防止颗粒和腐蚀问题。

公开(公告)号：US20140327141A1

公开(公告)日：2014-11-06

申请号：US14332866

申请日：2014-07-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chen-Hua YU ,  Shau-Lin SHUE ,  Hsiang-Huan LEE ,  Ching-Fu YEH

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76858 ,  H01L21/76871 ,  H01L21/76879 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/53271 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A copper interconnect structure in a semiconductor device comprises a dielectric layer having sidewalls and a surface defining an opening in the dielectric layer. The copper interconnect structure also comprises a barrier layer deposited on the sidewalls and the surface of the dielectric layer defining the opening. The copper interconnect structure further comprises a barrier/seed mixed layer deposited on the barrier layer. The copper interconnect structure additionally comprises an adhesive layer deposited on the barrier/seed mixed layer. The copper interconnect structure also comprises a seed layer deposited on the adhesive layer.

Abstract translation: 半导体器件中的铜互连结构包括具有侧壁和在电介质层中限定开口的表面的电介质层。 铜互连结构还包括沉积在限定开口的侧壁和介电层的表面上的阻挡层。 铜互连结构还包括沉积在阻挡层上的阻挡/种子混合层。 铜互连结构还包括沉积在阻挡/种子混合层上的粘合剂层。 铜互连结构还包括沉积在粘合剂层上的种子层。