公开(公告)号：US12085777B2

公开(公告)日：2024-09-10

申请号：US17398468

申请日：2021-08-10

申请人： Huawei Technologies Co., Ltd.

发明人： Ming Li ,  Jianmin Gong ,  Dongyu Geng ,  Francis Man

IPC分类号： G02B7/04 ,  G02B13/00 ,  G02B17/08 ,  G03B17/17

CPC分类号： G02B7/04 ,  G02B13/0065 ,  G02B17/08 ,  G03B17/17

摘要： This application provides a zoom assembly, including a first refraction component and a first lens apparatus. The first refraction component is configured to change a transmission path of light, and the first refraction component includes a first surface, a second surface, a third surface, and a first reflection structure. The three surfaces of the first refraction component are all transmission surfaces. An optical axis of the first lens apparatus is perpendicular to the second surface of the first refraction component. The first reflection structure is attached to the third surface, and is configured to receive light transmitted by one of the transmission surfaces and reflect the light to another transmission surface.

公开(公告)号：US12082510B2

公开(公告)日：2024-09-03

申请号：US17377737

申请日：2021-07-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Fan Huang ,  Kai-Wen Cheng ,  Chen-Chiu Huang ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC分类号： H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10

CPC分类号： H10N50/80 ,  H10B61/00 ,  H10B61/22 ,  H10N50/01 ,  H10N50/10

摘要： A semiconductor device comprises a first conductive feature on a semiconductor substrate, a bottom electrode on the first conductive feature, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and a top electrode on the MTJ stack. A spacer contacts a sidewall of the top electrode, a sidewall of the MTJ stack, and a sidewall of the bottom electrode. A conductive feature contacts the top electrode.

公开(公告)号：US12082305B2

公开(公告)日：2024-09-03

申请号：US17401963

申请日：2021-08-13

申请人： Huawei Technologies Co., Ltd.

发明人： Xiaoying Xu ,  Hui Ni ,  Zhenzhen Cao ,  Qufang Huang

IPC分类号： H04W80/02 ,  H04L1/1812 ,  H04W28/06

CPC分类号： H04W80/02 ,  H04L1/1819 ,  H04W28/06

摘要： An entity establishment processing method and an apparatus are provided. The processing method includes: A terminal side device receives first indication information from a first network side device, where the first indication information is used to trigger reestablishment of a first PDCP entity of the terminal side device. When a first bearer corresponding to the first PDCP entity is not a radio bearer used to perform duplication transmission between the terminal side device and a core network side device, in a process in which the terminal side device reestablishes the first PDCP entity based on the first indication information, the terminal side device sets a parameter of the first PDCP entity to an initial value.

公开(公告)号：US12081253B2

公开(公告)日：2024-09-03

申请号：US18352424

申请日：2023-07-14

申请人： STMicroelectronics S.r.l.

发明人： Nunzio Spina ,  Giuseppe Palmisano ,  Alessandro Castorina

IPC分类号： H04B1/16 ,  H03F3/19 ,  H03F3/24 ,  H04L27/06

CPC分类号： H04B1/16 ,  H03F3/19 ,  H03F3/245 ,  H04L27/06 ,  H03F2200/451

摘要： A method for calibrating the DC operating point of a PWM receiver circuit is disclosed. The PWM receiving circuit includes an envelope detector having a first resistor string, and includes a bias circuit having a second resistor string and a plurality of switches. The second resistor string is coupled between a supply voltage and a reference voltage and functions as a voltage divider. Each switch, when closed, accesses a second voltage at a node of the second resistor string connected to the closed switch. To perform the calibration process, the plurality of switches is closed one at a time, and the second voltage is compared with a first voltage at a first node of the first resistor string. The switch that, when closed, produces the smallest difference between the first voltage and the second voltage remains closed after the calibration process, and is used for demodulating the PWM signal.

公开(公告)号：US12080834B2

公开(公告)日：2024-09-03

申请号：US17270761

申请日：2019-08-09

申请人： OSRAM OLED GmbH

发明人： Simon Jerebic ,  Daniel Leisen ,  Philipp Pust ,  Thomas Birke

IPC分类号： H01L33/50 ,  H01L25/075 ,  H01L33/24 ,  H01L33/60

CPC分类号： H01L33/505 ,  H01L25/0753 ,  H01L33/24 ,  H01L33/60 ,  H01L2933/0041

摘要： In an embodiment an optoelectronic lighting device includes a carrier, exactly one light-emitting optoelectronic semiconductor component, wherein the semiconductor component has a light emission area on at least one surface side, and wherein the semiconductor component is arranged on an upper side of the carrier, at least one functional layer arranged above the light emission area and/or adjacent to the light emission area and an edging for the functional layer, wherein the edging surrounds the functional layer when viewed in a circumferential direction, the circumferential direction being parallel to the upper side of the carrier around the functional layer, and wherein the edging is formed of a transparent material.

公开(公告)号：US12080770B2

公开(公告)日：2024-09-03

申请号：US18065166

申请日：2022-12-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC分类号： H01L21/8234 ,  H01L21/265 ,  H01L21/324 ,  H01L21/768 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285

CPC分类号： H01L29/41791 ,  H01L21/265 ,  H01L21/324 ,  H01L21/76814 ,  H01L21/76897 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/28518 ,  H01L21/76804 ,  H01L29/66545 ,  H01L29/7848

摘要： A semiconductor device and method of manufacture are provided. A source/drain region is formed next to a spacer, which is adjacent to a gate electrode. An implantation is performed through an implantation mask into the source/drain region as well as the first spacer, forming an implantation region within the spacer.

公开(公告)号：US12080713B2

公开(公告)日：2024-09-03

申请号：US18358140

申请日：2023-07-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Hsun Chiu ,  Ching-Wei Tsai ,  Yu-Xuan Huang ,  Cheng-Chi Chuang ,  Shang-Wen Chang

IPC分类号： H01L27/088 ,  H01L21/768 ,  H01L23/535 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L27/0886 ,  H01L21/7682 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7851

摘要： Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.

公开(公告)号：US12080684B2

公开(公告)日：2024-09-03

申请号：US17808774

申请日：2022-06-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Chung-Hao Tsai ,  Chuei-Tang Wang

IPC分类号： H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L21/566 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/09 ,  H01L24/17 ,  H01L24/32 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2924/1434

摘要： A method includes thinning a semiconductor substrate of a device die to reveal through-substrate vias that extend into the semiconductor substrate, and forming a first redistribution structure, which includes forming a first plurality of dielectric layers over the semiconductor substrate, and forming a first plurality of redistribution lines in the first plurality of dielectric layers. The first plurality of redistribution lines are electrically connected to the through-substrate vias. The method further includes placing a first memory die over the first redistribution structure, and forming a first plurality of metal posts over the first redistribution structure. The first plurality of metal posts are electrically connected to the first plurality of redistribution lines. The first memory die is encapsulated in a first encapsulant. A second plurality of redistribution lines are formed over, and electrically connected to, the first plurality of metal posts and the first memory die.

公开(公告)号：US12080599B2

公开(公告)日：2024-09-03

申请号：US17959557

申请日：2022-10-04

申请人： Tokyo Electron Limited

发明人： Junling Sun ,  Lior Huli ,  Andrew Metz ,  Angelique Raley

IPC分类号： H01L21/768 ,  H01L21/3105 ,  H01L21/311

CPC分类号： H01L21/76897 ,  H01L21/31051 ,  H01L21/31116 ,  H01L21/76832

摘要： Methods and improved process flows are provided herein for forming self-aligned contacts using spin-on silicon carbide (SiC). More specifically, the disclosed methods and process flows form self-aligned contacts by using spin-on SiC as a cap layer for at least one other structure, instead of depositing a SiC layer via plasma vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The other structure may be a source and drain contact made through the use of a trench conductor. By utilizing spin-on SiC as a cap layer material, the disclosed methods and process flows avoid problems that typically occur when SiC is deposited, for example by CVD, and subsequently planarized. As such, the disclosed methods and process flows improve upon conventional methods and process flows for forming self-aligned contacts by reducing defectivity and improving yield.

公开(公告)号：US12080563B2

公开(公告)日：2024-09-03

申请号：US17994841

申请日：2022-11-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chien-Hsun Chen ,  Yu-Min Liang ,  Yen-Ping Wang ,  Jiun Yi Wu ,  Chen-Hua Yu ,  Kai-Chiang Wu

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538

CPC分类号： H01L21/486 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/5226

摘要： Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.