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公开(公告)号：US20230260801A1
公开(公告)日：2023-08-17
申请号：US17718955
申请日：2022-04-12
IPC分类号： H01L21/321 , H01L21/311 , H01L21/3213 , H01L21/67
CPC分类号： H01L21/3212 , H01L21/31116 , H01L21/32136 , H01L21/31144 , H01L21/32139 , H01L21/67167
摘要： A method of processing a substrate that includes: etching a recess in the substrate using a metal hard mask (MHM) layer as an etch mask, the substrate including a dielectric layer over a conductive layer the includes a first conductive material, a portion of the MHM layer remaining over top surfaces of the dielectric layer after the etching; depositing a sacrificial fill over the substrate to at least partially fill the recess; removing the remaining portion of the MHM layer to expose the top surfaces while protecting the recess with the sacrificial fill; removing the sacrificial fill from the recess after removing the MHM layer, the removing of the sacrificial fill including exposing a portion of the conductive layer; and depositing a second conductive material to fill the recess, the depositing of the second conductive material providing an electrical connection between the conductive layer and the second conductive material.
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公开(公告)号：US20230197505A1
公开(公告)日：2023-06-22
申请号：US17644932
申请日：2021-12-17
发明人： Katie Lutker-Lee , Angelique Raley , Nicholas Joy
IPC分类号： H01L21/768 , H01L21/027 , G03F7/095 , G03F1/22 , G03F7/20
CPC分类号： H01L21/76811 , H01L21/0274 , H01L21/76877 , G03F7/095 , G03F1/22 , G03F7/2004
摘要： A method for patterning a substrate includes: forming a first photoresist etch mask with an extreme ultraviolet (EUV) lithography process, the first photoresist etch mask including first through openings, the first photoresist etch mask including a metal-based photoresist material; forming a second photoresist etch mask over the first photoresist etch mask, the second photoresist etch mask including second through openings; and forming first openings, through the first and the second photoresist etch masks, in a region of the substrate that vertically overlaps both the first through openings and the second through openings.
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公开(公告)号：US20230078946A1
公开(公告)日：2023-03-16
申请号：US17943729
申请日：2022-09-13
发明人： Steven Grzeskowiak , Lior Huli , Angelique Raley , Cong Que Dinh , Makoto Muramatsu , Seiji Nagahara
摘要： A method of microfabrication includes depositing a photoresist film on a working surface of a semiconductor wafer, the photoresist film being sensitive to extreme ultraviolet radiation; exposing the photoresist film to a pattern of extreme ultraviolet radiation; performing a hybrid develop of the photoresist film. The hybrid develop includes executing a first development process to remove a first portion of the photoresist film; stopping the development of the photoresist film after the first development process, the photo resist film including a structure having a first critical dimension larger than a target critical dimension after the stopping; and after stopping the development, executing a second development process to remove a second portion of the photoresist film and shrinking the critical dimension of the structure from the first critical dimension to a second critical dimension that is less than the first critical dimension.
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公开(公告)号：US20230054125A1
公开(公告)日：2023-02-23
申请号：US17406612
申请日：2021-08-19
发明人： Choong-man Lee , Soo Doo Chae , Angelique Raley , Qiaowei Lou , Toshio Hasegawa , Yoshihiro Kato
IPC分类号： H01L21/033 , H01L21/027 , H01L21/311
摘要： A method for fabricating a semiconductor device is described that includes forming a base layer over a top layer of a substrate, the base layer includes a silicon based dielectric having a thickness less than or equal to 5 nm and greater than or equal to 0.5 nm; forming a photoresist layer over the base layer, the photoresist including a first side and an opposite second side; exposing a first portion of the photoresist layer to a pattern of extreme ultraviolet (EUV) radiation from the first side; exposing a second portion of the photoresist layer with a pattern of electron flux from the second side, the electron flux being directed into the photoresist layer from the base layer in response to the EUV radiation; developing the exposed photoresist layer to form a patterned photoresist layer; and transferring the pattern of the patterned photoresist layer to the base layer and the top layer.
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公开(公告)号：US11515203B2
公开(公告)日：2022-11-29
申请号：US16782344
申请日：2020-02-05
发明人： Yen-Tien Lu , Kai-Hung Yu , Xinghua Sun , Angelique Raley
IPC分类号： H01L21/768 , H01L21/02 , H01L21/67 , H01L21/311
摘要： Methods and systems for selective deposition of conductive a cap for FAV features are described. In an embodiment, a method may include receiving a substrate having an interlayer dielectrics (ILD) layer, the ILD layer having a recess, the recess having a conductive layer formed therein, the conductive layer comprising a first conductive material. Additionally, such a method may include forming a cap within a region defined by the recess and in contact with a surface of the conductive layer, the cap comprising a second conductive material. The method may also include forming a conformal etch stop layer in contact with a surface of the cap and in contact with a region of the ILD layer. Further, the method may include selectively etching the etch stop layer using a plasma etch process, wherein the plasma etch process removes the etch stop layer selective to the second conductive material comprising the cap.
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公开(公告)号：US20220262679A1
公开(公告)日：2022-08-18
申请号：US17177379
申请日：2021-02-17
发明人： Junling Sun , Lior Huli , Andrew Metz , Angelique Raley
IPC分类号： H01L21/768 , H01L21/311 , H01L21/3105
摘要： Methods and improved process flows are provided herein for forming self-aligned contacts using spin-on silicon carbide (SiC). More specifically, the disclosed methods and process flows form self-aligned contacts by using spin-on SiC as a cap layer for at least one other structure, instead of depositing a SiC layer via plasma vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The other structure may be a source and drain contact made through the use of a trench conductor. By utilizing spin-on SiC as a cap layer material, the disclosed methods and process flows avoid problems that typically occur when SiC is deposited, for example by CVD, and subsequently planarized. As such, the disclosed methods and process flows improve upon conventional methods and process flows for forming self-aligned contacts by reducing defectivity and improving yield.
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公开(公告)号：US20210151350A1
公开(公告)日：2021-05-20
申请号：US17088136
申请日：2020-11-03
发明人： Yen-Tien Lu , Angelique Raley , Joe Lee
IPC分类号： H01L21/768 , H01L21/027
摘要： Split ash processes are disclosed to suppress damage to low-dielectric-constant (low-K) layers during via formation. For one embodiment, ash processes used to remove an organic layer, such as an organic planarization layer (OPL), associated with via formation are split into multiple ash process steps that are separated by intervening process steps. A first ash process is performed to remove a portion of an organic layer after vias have been partially opened to a low-K layer. Subsequently, after the vias are fully opened through the low-K layer, an additional ash process is performed to remove the remaining organic material. Although some damage may still occur on via sidewalls due to this split ash processing, the damage is significantly reduced as compared to prior solutions, and device performance is improved. Target critical dimension (CD) for vias and effective dielectric constants for the low-K layer are achieved.
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公开(公告)号：US20210020448A1
公开(公告)日：2021-01-21
申请号：US16513602
申请日：2019-07-16
发明人： Qiaowei Lou , Angelique Raley , Alok Ranjan
IPC分类号： H01L21/3105 , H01L21/311 , H01L21/02
摘要： Described herein is an innovative method smoothing substrate surfaces. The surfaces to be smoothed may be a surface of a patterned feature of the substrate or may be an unpatterned surface of the substrate. The techniques disclosed utilize atomic layer deposition (ALD) techniques to smooth surfaces. For example, the use of ALD to smooth the line edge roughness of a patterned feature or roughness of a surface of an unpatterned layer is described. ALD can grow high quality films with atomic level thickness controllability and conformality. The rough, sharp asperities on patterned features (for example on sidewalls or tops of a patterned feature) or on a surface can be smoothed by precisely growing material layer by layer over the rough surface. Thus, asperities on a surface may be smoothed, improving the manufacturability and/or device performance.
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9.发明授权公开(公告)号：US10727057B2
公开(公告)日：2020-07-28
申请号：US16356477
申请日：2019-03-18
IPC分类号： H01L21/00 , H01L21/033 , H01L21/308 , H01L21/677 , H01L21/67 , H01L21/66
摘要： A method is provided for self-aligned multi-patterning on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting film-forming modules, etching modules, and transfer modules. A workpiece having a mandrel pattern formed thereon is received into the common manufacturing platform. A sidewall spacer pattern is formed based, at least in part, on the mandrel pattern, the sidewall spacer pattern having a plurality of second features separated by a second pitch distance with the first pitch distance being greater than the second pitch distance. The integrated sequence of processing steps is executed within the common manufacturing platform without leaving the controlled environment and the transfer modules are used to transfer the workpiece between the processing modules while maintaining the workpiece within the controlled environment. Broadly, using selective/conformal deposition, etching, or implanting techniques to form a sidewall spacer pattern on a common manufacturing platform.
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公开(公告)号：US20200051859A1
公开(公告)日：2020-02-13
申请号：US16508923
申请日：2019-07-11
发明人： Xinghua Sun , Yen-Tien Lu , Angelique Raley , David O'Meara , Jeffrey Smith
IPC分类号： H01L21/768 , H01L21/02
摘要： Methods are disclosed that provide improved via profile control by forming atomic layer deposition (ALD) liners to protect side walls of vias during subsequent etch processes. ALD liners can be used for BEOL etch processes as well as for full self-aligned via (FSAV) processes and/or other processes. For one embodiment, ALD liners are used as protection or sacrificial layers for vias to reduce damage during multilayer via or trench etch processes. The ALD liners can also be deposited at different points within process flows, for example, before or after removal of organic planarization layers. The use of ALD liners facilitates shrinking of via critical dimensions (CDs) while still controlling via profiles for various process applications including dual Damascene processes and FSAV processes. In addition, the use of ALD liners improves overall CD control for via or hole formation as well as device yield and reliability.
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