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公开(公告)号：US20190333763A1
公开(公告)日：2019-10-31
申请号：US16396360
申请日：2019-04-26
IPC分类号： H01L21/02
摘要： A method of area selective deposition for cap layer formation in advanced semiconductor contacts. The method includes providing a planarized substrate including a first dielectric layer and a first metal layer, oxidizing a surface of the first metal layer to form an oxidized metal layer, and selectively depositing a second dielectric layer on the oxidized metal layer. The selectively depositing the second dielectric layer can include moving the planarized substrate below a gas inlet dispensing a deposition gas during a spatial vapor phase deposition process, where the deposition gas is preferentially exposed to the oxidized metal layer extending above a surface of the first dielectric layer.
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2.发明授权公开(公告)号：US11621190B2
公开(公告)日：2023-04-04
申请号：US17334389
申请日：2021-05-28
发明人： Kai-Hung Yu , David O'Meara , Nicholas Joy , Gyanaranjan Pattanaik , Robert Clark , Kandabara Tapily , Takahiro Hakamata , Cory Wajda , Gerrit Leusink
IPC分类号： H01L21/768 , H01L21/02
摘要： A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.
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公开(公告)号：US20230260801A1
公开(公告)日：2023-08-17
申请号：US17718955
申请日：2022-04-12
IPC分类号： H01L21/321 , H01L21/311 , H01L21/3213 , H01L21/67
CPC分类号： H01L21/3212 , H01L21/31116 , H01L21/32136 , H01L21/31144 , H01L21/32139 , H01L21/67167
摘要： A method of processing a substrate that includes: etching a recess in the substrate using a metal hard mask (MHM) layer as an etch mask, the substrate including a dielectric layer over a conductive layer the includes a first conductive material, a portion of the MHM layer remaining over top surfaces of the dielectric layer after the etching; depositing a sacrificial fill over the substrate to at least partially fill the recess; removing the remaining portion of the MHM layer to expose the top surfaces while protecting the recess with the sacrificial fill; removing the sacrificial fill from the recess after removing the MHM layer, the removing of the sacrificial fill including exposing a portion of the conductive layer; and depositing a second conductive material to fill the recess, the depositing of the second conductive material providing an electrical connection between the conductive layer and the second conductive material.
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公开(公告)号：US20240363333A1
公开(公告)日：2024-10-31
申请号：US18309521
申请日：2023-04-28
IPC分类号： H01L21/02 , H01L21/56 , H01L21/683
CPC分类号： H01L21/02118 , H01L21/0206 , H01L21/02282 , H01L21/02299 , H01L21/56 , H01L21/6835 , H01L21/31133
摘要： In certain embodiments, a method of microfabrication includes depositing a 2D polymer material over a substrate surface having a first material and a second material such that the 2D polymer adheres to the first material without adhering to the second material. The method further includes depositing a target material over the second material. The 2D material adhered to the first material inhibits deposition of the target material over the first material. The method further includes removing the 2D polymer material.
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公开(公告)号：US20230075263A1
公开(公告)日：2023-03-09
申请号：US17863594
申请日：2022-07-13
发明人： Soo Doo Chae , Sang Cheol Han , Hojin Kim , Kandabara Tapily , Satohiko Hoshino , Adam Gildea , Gerrit Leusink
IPC分类号： H01L23/00
摘要： A semiconductor package is disclosed. The semiconductor package includes a first substrate including a first interconnect structure and a first bonding layer adjacent the first interconnect structure. The semiconductor package includes a second substrate including a second interconnect structure and a second bonding layer adjacent the second interconnect structure. The first bonding layer and second bonding layer each include a metal oxide.
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公开(公告)号：US20230051311A1
公开(公告)日：2023-02-16
申请号：US17884371
申请日：2022-08-09
IPC分类号： H01L23/532 , H01L21/768 , H01L23/522
摘要： A method of forming a metal superlattice structure includes depositing, on a substrate, a layer of a first metal with face-centered-cubic (fcc) crystal structure. The method further includes depositing a layer of ruthenium (Ru) metal with fcc crystal structure on the layer of the first metal. The layer of the first metal may cause the layer of ruthenium metal to have fcc crystal structure.
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公开(公告)号：US20230009688A1
公开(公告)日：2023-01-12
申请号：US17854930
申请日：2022-06-30
发明人： Dina H. Triyoso , Lior Huli , Corey Lemley , Robert D. Clark , Gerrit Leusink
IPC分类号： H01L21/768 , H01L21/02 , H01L21/321 , H01L21/3213 , H01L21/687
摘要： A method of processing a substrate that includes: loading the substrate in a processing system, the substrate including a metal having a metal surface and a first dielectric material having a dielectric material surface, the metal surface and the dielectric material surface being at the same level; etching the metal to form a recessed metal surface below the dielectric material surface; selectively forming a self-assembled monolayer (SAM) on the recessed metal surface using a spin-on process; and depositing a dielectric film including a second dielectric material on the dielectric material surface.
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8.发明授权公开(公告)号：US11024535B2
公开(公告)日：2021-06-01
申请号：US16598772
申请日：2019-10-10
发明人： Kai-Hung Yu , David O'Meara , Nicholas Joy , Gyanaranjan Pattanaik , Robert Clark , Kandabara Tapily , Takahiro Hakamata , Cory Wajda , Gerrit Leusink
IPC分类号： H01L21/768
摘要： A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.
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公开(公告)号：US20240153781A1
公开(公告)日：2024-05-09
申请号：US18385522
申请日：2023-10-31
发明人： Hisashi Higuchi , Kai-Hung Yu , Cory Wajda , Gyanaranjan Pattanaik , Kandabara Tapily , Gerrit Leusink , Robert Clark
IPC分类号： H01L21/3213 , H01L21/02 , H01L21/311
CPC分类号： H01L21/32136 , H01L21/02175 , H01L21/02244 , H01L21/02252 , H01L21/02337 , H01L21/31122
摘要： Embodiments of methods are provided for thermal dry etching of a ruthenium (Ru) metal layer. In the disclosed embodiments, a substrate containing a Ru metal layer formed thereon is exposed to a gas pulse sequence, while the substrate is held at a relatively high substrate temperature (e.g., a temperature greater than or equal to about 160° C.), to provide thermal etching of the Ru metal layer. As described further herein, the gas pulse sequence may generally include a plurality of gas pulses, which are supplied to the substrate sequentially with substantially no overlap between gas pulses. The gas pulses supplied to the substrate form: (i) volatile reaction products that are vaporized from the Ru surface, and (ii) non-volatile oxide surface layers that are removed from the Ru surface by the next gas pulse, resulting in atomic layer etching (ALE) of the Ru metal layer.
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公开(公告)号：US11170992B2
公开(公告)日：2021-11-09
申请号：US16396360
申请日：2019-04-26
发明人： Kandabara Tapily , Gerrit Leusink
IPC分类号： H01L21/02 , H01L21/768 , H01L21/285
摘要： A method of area selective deposition for cap layer formation in advanced semiconductor contacts. The method includes providing a planarized substrate including a first dielectric layer and a first metal layer, oxidizing a surface of the first metal layer to form an oxidized metal layer, and selectively depositing a second dielectric layer on the oxidized metal layer. The selectively depositing the second dielectric layer can include moving the planarized substrate below a gas inlet dispensing a deposition gas during a spatial vapor phase deposition process, where the deposition gas is preferentially exposed to the oxidized metal layer extending above a surface of the first dielectric layer.
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