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公开(公告)号：US20220037162A1
公开(公告)日：2022-02-03
申请号：US16944563
申请日：2020-07-31
发明人： David O'Meara , Anthony Dip , Masanobu Igeta
IPC分类号： H01L21/3105 , C23C16/455 , C23C16/458
摘要： Methods are provided for planarizing a patterned substrate in a spatial atomic layer processing system comprising a rotating platen. The patterned substrate may generally include features having higher regions and lower regions. To planarize the patterned substrate, or reduce a height differential between the higher and lower regions, a selective atomic layer etching (ALE) process is disclosed to preferentially form a modified layer on the higher regions of the features by exposing a surface of the patterned substrate to a precursor gas while the rotating platen spins at a high rotational speed. By preferentially forming the modified layer on the higher regions of the features, and subsequently removing the modified layer, the selective ALE process described herein preferentially etches the higher regions of the features to lessen the height differential between the higher and lower regions until a desired planarization of the features is achieved.
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公开(公告)号：US20200051859A1
公开(公告)日：2020-02-13
申请号：US16508923
申请日：2019-07-11
发明人： Xinghua Sun , Yen-Tien Lu , Angelique Raley , David O'Meara , Jeffrey Smith
IPC分类号： H01L21/768 , H01L21/02
摘要： Methods are disclosed that provide improved via profile control by forming atomic layer deposition (ALD) liners to protect side walls of vias during subsequent etch processes. ALD liners can be used for BEOL etch processes as well as for full self-aligned via (FSAV) processes and/or other processes. For one embodiment, ALD liners are used as protection or sacrificial layers for vias to reduce damage during multilayer via or trench etch processes. The ALD liners can also be deposited at different points within process flows, for example, before or after removal of organic planarization layers. The use of ALD liners facilitates shrinking of via critical dimensions (CDs) while still controlling via profiles for various process applications including dual Damascene processes and FSAV processes. In addition, the use of ALD liners improves overall CD control for via or hole formation as well as device yield and reliability.
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3.发明授权公开(公告)号：US11621190B2
公开(公告)日：2023-04-04
申请号：US17334389
申请日：2021-05-28
发明人： Kai-Hung Yu , David O'Meara , Nicholas Joy , Gyanaranjan Pattanaik , Robert Clark , Kandabara Tapily , Takahiro Hakamata , Cory Wajda , Gerrit Leusink
IPC分类号： H01L21/768 , H01L21/02
摘要： A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.
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公开(公告)号：US20220189781A1
公开(公告)日：2022-06-16
申请号：US17514233
申请日：2021-10-29
发明人： Shihsheng Chang , David O'Meara , Andrew Metz , Yun Han
IPC分类号： H01L21/3065 , H01J37/305 , H01L21/02 , H01J37/32 , H01L21/033
摘要： Improved process flows and methods are provided herein for forming a passivation layer on sidewall surfaces of openings formed in an amorphous carbon layer (ACL) to avoid bowing during an ACL etch process. More specifically, improved process flows and methods are provided to form a silicon-containing passivation layer on sidewall surfaces of the openings created within the ACL without utilizing atomic layer deposition (ALD) techniques or converting the silicon-containing passivation layer to an oxide or a nitride. As such, the improved process flows and methods disclosed herein may be used to protect the sidewall surfaces of the ACL and prevent bowing during the ACL etch process, while also reducing processing time and improving throughput.
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公开(公告)号：US10964587B2
公开(公告)日：2021-03-30
申请号：US16415687
申请日：2019-05-17
发明人： Yen-Tien Lu , David O'Meara , Angelique Raley , Xinghua Sun
IPC分类号： H01L21/768 , H01L21/762 , H01L21/308
摘要： An atomic layer deposition (ALD) technique is used to deposit one or more layers on hard mask layers and the sidewalls of low-K dielectric trench as part of the trench etch process. The ALD layer(s) can prevent the hard mask from being eroded during various hard mask open processes. Further, the ALD layer(s) may be utilized to prevent the low-K dielectric sidewall from being laterally etched during the low-K dielectric trench etch. Hence, better control of the trench profile and better critical dimension control may be provided.
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公开(公告)号：US11195723B1
公开(公告)日：2021-12-07
申请号：US17119019
申请日：2020-12-11
发明人： Shihsheng Chang , David O'Meara , Andrew Metz , Yun Han
IPC分类号： H01L21/3065 , H01L21/033 , H01J37/305 , H01J37/32 , H01L21/02
摘要： Improved process flows and methods are provided herein for forming a passivation layer on sidewall surfaces of openings formed in an amorphous carbon layer (ACL) to avoid bowing during an ACL etch process. More specifically, improved process flows and methods are provided to form a silicon-containing passivation layer on sidewall surfaces of the openings created within the ACL without utilizing atomic layer deposition (ALD) techniques or converting the silicon-containing passivation layer to an oxide or a nitride. As such, the improved process flows and methods disclosed herein may be used to protect the sidewall surfaces of the ACL and prevent bowing during the ACL etch process, while also reducing processing time and improving throughput.
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7.发明申请公开(公告)号：US20210287936A1
公开(公告)日：2021-09-16
申请号：US17334389
申请日：2021-05-28
发明人： Kai-Hung Yu , David O'Meara , Nicholas Joy , Gyanaranjan Pattanaik , Robert Clark , Kandabara Tapily , Takahiro Hakamata , Cory Wajda , Gerrit Leusink
IPC分类号： H01L21/768
摘要： A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.
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8.发明公开公开(公告)号：US20240047218A1
公开(公告)日：2024-02-08
申请号：US18380776
申请日：2023-10-17
发明人： David O'Meara , Anthony Dip , Masanobu Igeta
IPC分类号： H01L21/3105 , C23C16/458 , C23C16/455
CPC分类号： H01L21/31055 , C23C16/4584 , C23C16/45553
摘要： Atomic layer processing systems are provided for planarizing a patterned substrate utilizing a rotating platen. An atomic layer processing system may include a spatial atomic layer processing chamber with the rotating platen, a sensor that provides sensor data related to a property of the patterned substrate and/or a reaction in the spatial atomic layer processing chamber, and a controller. The controller may be coupled to the sensor to receive the sensor data and utilize such data to adjust at least one operating parameter of the atomic layer processing system so as to achieve a desired amount of planarization of the patterned substrate.
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9.发明申请公开(公告)号：US20220076942A1
公开(公告)日：2022-03-10
申请号：US17014515
申请日：2020-09-08
发明人： Katie Lutker-Lee , David O'Meara , Angelique Raley
IPC分类号： H01L21/027 , H01L21/02 , H01L21/311
摘要： Improved process flows and methods are provided herein for trimming structures formed on a patterned substrate. In the disclosed process flows and methods, a self-aligned multiple patterning (SAMP) process is utilized for patterning structures, such as mandrels, on a substrate. After the structures are patterned, an atomic layer deposition (ALD) process is used to form a spacer layer on the patterned structures. In the SAMP process disclosed herein, a critical dimension (CD) of the patterned structures is trimmed concurrently with, and as a result of, the formation of the spacer layer by controlling various ALD process parameters and conditions. By trimming the patterned structures in situ of the ALD chamber used to form the spacer layer on the patterned structures, the improved process flows and methods described herein provide a CD trim method that does not adversely affect the pattern profile or process throughput.
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公开(公告)号：US11164781B2
公开(公告)日：2021-11-02
申请号：US16508923
申请日：2019-07-11
发明人： Xinghua Sun , Yen-Tien Lu , Angelique Raley , David O'Meara , Jeffrey Smith
IPC分类号： H01L21/768 , H01L21/02
摘要： Methods are disclosed that provide improved via profile control by forming atomic layer deposition (ALD) liners to protect side walls of vias during subsequent etch processes. ALD liners can be used for BEOL etch processes as well as for full self-aligned via (FSAV) processes and/or other processes. For one embodiment, ALD liners are used as protection or sacrificial layers for vias to reduce damage during multilayer via or trench etch processes. The ALD liners can also be deposited at different points within process flows, for example, before or after removal of organic planarization layers. The use of ALD liners facilitates shrinking of via critical dimensions (CDs) while still controlling via profiles for various process applications including dual Damascene processes and FSAV processes. In addition, the use of ALD liners improves overall CD control for via or hole formation as well as device yield and reliability.
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