公开(公告)号：US12183697B2

公开(公告)日：2024-12-31

申请号：US18329128

申请日：2023-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Yen-Ming Chen ,  Chih-Sheng Li ,  Hui-Chi Chen ,  Chih-Hung Lu ,  Dian-Hau Chen

IPC: H01L23/00 ,  H01L21/02

Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method includes depositing a first dielectric layer over a metal pad disposed over a workpiece, forming a first opening in the first dielectric layer to expose a portion of the metal pad, after the forming of the first opening, forming a second dielectric layer over the exposed portion of the metal pad, depositing a first polymeric material over the second dielectric layer, forming a second opening through the first polymeric material and the second dielectric layer to expose the metal pad, and forming a bump feature over the exposed metal pad.

公开(公告)号：US20240373758A1

公开(公告)日：2024-11-07

申请号：US18772445

申请日：2024-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Kai-Wen Cheng ,  Chen-Chiu Huang ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10

Abstract: A semiconductor device comprises a first conductive feature on a semiconductor substrate, a bottom electrode on the first conductive feature, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and a top electrode on the MTJ stack. A spacer contacts a sidewall of the top electrode, a sidewall of the MTJ stack, and a sidewall of the bottom electrode. A conductive feature contacts the top electrode.

公开(公告)号：US11716910B2

公开(公告)日：2023-08-01

申请号：US17002098

申请日：2020-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Hsiang-Ku Shen ,  Liang-Wei Wang ,  Chen-Chiu Huang ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/22 ,  H10N50/01

Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch slop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer.

公开(公告)号：US20220069199A1

公开(公告)日：2022-03-03

申请号：US17002098

申请日：2020-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Hsiang-Ku Shen ,  Liang-Wei Wang ,  Chen-Chiu Huang ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch stop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer

公开(公告)号：US11145564B2

公开(公告)日：2021-10-12

申请号：US16395435

申请日：2019-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Hui-Chi Chen ,  Kuo-Chin Chang ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  H01L21/56

Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method for integrated circuit (IC) fabrication includes forming a passivation layer over a first contact feature, forming a second contact feature over and through the passivation layer to electrically connect to the first contact feature, and forming a multi-layer passivation structure over the second contact feature and over the passivation layer. Forming the multi-layer passivation structure includes depositing a first nitride layer, an oxide layer over the first nitride layer, and a second nitride layer over the oxide layer.

公开(公告)号：US20210265291A1

公开(公告)日：2021-08-26

申请号：US16798749

申请日：2020-02-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Dian-Hau Chen ,  Mao-Nan Wang ,  Tzu-Li Lee ,  Yen-Ming Chen ,  Tzung-Luen Li

IPC: H01L23/00 ,  H01L23/498

Abstract: In some embodiments, the present disclosure relates to a method including forming an interconnect structure over a substrate. A bond pad may be coupled to the interconnect structure, and a polymeric material may be deposited over the bond pad. In some embodiments, the method further includes performing a patterning process to remove a portion of the polymeric material to form an opening in the polymeric material. The opening directly overlies and exposes the bond pad. Further, the method includes a first cleaning process. The polymeric material is cured to form a polymeric protection layer, and a second cleaning process is performed.

公开(公告)号：US20240213305A1

公开(公告)日：2024-06-27

申请号：US18594864

申请日：2024-03-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Hung-Chao Kao ,  Yuan-Yang Hsiao ,  Tsung-Chieh Hsiao ,  Hsiang-Ku Shen ,  Hui-Chi Chen ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01G4/005 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H10B61/00

CPC classification number: H01L28/60 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76805 ,  H01L23/5226 ,  H10B61/10

Abstract: The present disclosure is directed to a semiconductor device. The semiconductor device includes a multi-layer interconnect structure disposed over a substrate, a dielectric layer disposed over the multi-layer interconnect structure, and a metal-insulator-metal (MIM) capacitor disposed over the dielectric layer. The MIM capacitor includes a bottom electrode disposed on a top surface of the dielectric layer, a top electrode disposed above the bottom electrode, and an insulating layer interposed between the bottom electrode and the top electrode. The bottom electrode has a slanted sidewall with respect to the top surface of the dielectric layer. The top electrode has a vertical sidewall with respect to the top surface of the dielectric layer. The insulating layer covers the slanted sidewall of the bottom electrode.

公开(公告)号：US20220384712A1

公开(公告)日：2022-12-01

申请号：US17884221

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Hsiang-Ku Shen ,  Liang-Wei Wang ,  Chen-Chiu Huang ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch stop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer

公开(公告)号：US11437331B2

公开(公告)日：2022-09-06

申请号：US16655998

申请日：2019-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Mao-Nan Wang ,  Hui-Chi Chen ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L23/00

Abstract: A chip structure is provided. The chip structure includes a semiconductor substrate. The chip structure includes a first dielectric layer over the semiconductor substrate. The chip structure includes a first conductive layer over the first dielectric layer. The chip structure includes a second dielectric layer over the first conductive layer and the first dielectric layer. The chip structure includes a first conductive via passing through the second dielectric layer, the first conductive layer, and the first dielectric layer and electrically connected to the first conductive layer. The chip structure includes a second conductive via passing through the second dielectric layer and the first dielectric layer. The chip structure includes a first conductive pad over and in direct contact with the first conductive via. The chip structure includes a second conductive pad over and in direct contact with the second conductive via.

公开(公告)号：US11031458B2

公开(公告)日：2021-06-08

申请号：US16593078

申请日：2019-10-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Chih-Yang Pai ,  Yuan-Yang Hsiao ,  Tsung-Chieh Hsiao ,  Hui-Chi Chen ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L49/02 ,  H01L23/64 ,  H01G4/10 ,  H01G4/012

Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a substrate, and the substrate includes a capacitor region and a non-capacitor region. The MIM capacitor structure includes a first electrode layer formed over the substrate, and a first spacer formed on a sidewall of the first electrode layer. The MIM capacitor structure includes a first dielectric layer formed on the first spacers, and a second electrode layer formed on the first dielectric layer. The second electrode layer extends from the capacitor region to the non-capacitor region, and the second electrode layer extends beyond an outer sidewall of the first spacer.