公开(公告)号：US09922725B2

公开(公告)日：2018-03-20

申请号：US15368402

申请日：2016-12-02

Applicant: INTEL CORPORATION

Inventor： Bruce Querbach ,  William K. Lui ,  David G. Ellis ,  David J. Zimmerman ,  Theodore Z. Schoenborn ,  Christopher W. Hampson ,  Ifar Wan ,  Yulan Zhang

IPC: G11C29/44 ,  G11C29/36 ,  G11C29/18 ,  G11C29/16 ,  G11C29/12 ,  G11C29/00 ,  G06F11/27 ,  G06F11/263 ,  G11C29/38 ,  G11C29/10 ,  G11C29/20 ,  G11C11/406

CPC classification number: G11C29/38 ,  G06F11/263 ,  G06F11/27 ,  G11C11/406 ,  G11C29/10 ,  G11C29/1201 ,  G11C29/16 ,  G11C29/18 ,  G11C29/20 ,  G11C29/36 ,  G11C29/4401 ,  G11C29/72 ,  G11C29/78 ,  G11C29/783 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/1206 ,  G11C2029/1208 ,  G11C2029/3602 ,  G11C2029/4402

Abstract: In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory. In one embodiment, data patterns are generated as a function of memory addresses and periodic address offsets.

公开(公告)号：US09875809B2

公开(公告)日：2018-01-23

申请号：US15224973

申请日：2016-08-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won-Hwa Shin

IPC: G11C29/00 ,  G11C29/44 ,  G11C29/52 ,  G11C29/36 ,  G11C29/38 ,  G11C7/10 ,  G11C11/4096

CPC classification number: G11C29/44 ,  G11C7/1006 ,  G11C11/4096 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/14 ,  G11C29/18 ,  G11C29/26 ,  G11C29/34 ,  G11C29/36 ,  G11C29/38 ,  G11C29/46 ,  G11C29/52 ,  G11C29/56008 ,  G11C29/56012 ,  G11C2029/4402 ,  G11C2029/5602 ,  G11C2207/107

Abstract: A memory device includes a controller, a multiplexer, a deserializer, a data modifier, a memory cell array and an error detector. The controller is configured to generate signals in response to an address signal and a command signal. The multiplexer is configured to output a clock signal as internal data signals when the test mode signal is activated. The deserializer is configured to deserialize N bit values included in the internal data signals to generate deserialized signals. The data modifier is configured to invert the deserialized signals to generate bit line signals in response to an inversion control signal and the data modifying signals. The memory cell array is configured to store the bit line signals to memory cells corresponding to the address signal. The error detector is configured to determine if an error exists in signals read from the memory cells and to output an error detecting signal.

公开(公告)号：US09870808B2

公开(公告)日：2018-01-16

申请号：US15295571

申请日：2016-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunui Lee ,  Won-joo Yun ,  Hye-seung Yu ,  In-dal Song

IPC: G11C7/00 ,  G11C7/12 ,  G06F3/06 ,  G11C7/22 ,  G11C8/08 ,  G11C8/14 ,  G11C29/12

CPC classification number: G11C7/12 ,  G06F3/0608 ,  G06F3/0652 ,  G06F3/0656 ,  G06F3/0673 ,  G06F13/4086 ,  G11C7/02 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/22 ,  G11C8/08 ,  G11C8/14 ,  G11C29/021 ,  G11C29/022 ,  G11C29/028 ,  G11C29/12 ,  G11C29/12005 ,  G11C29/1201 ,  G11C29/56012 ,  G11C2029/5602 ,  G11C2207/105

Abstract: Provided is a memory device configured to perform a calibration operation without having a ZQ pin. The memory device includes a calibration circuit configured to generate a pull-up calibration code and a pull-down calibration code which termination of a data input/output pad for impedance matching in the data input/output pad is controlled. The calibration circuit performs a first calibration operation for trimming first and second reference resistors based on an external resistor to be connected to a pad, and a second calibration operation for generating the pull-up calibration code and the pull-down calibration code based on the trimmed second reference resistor.

公开(公告)号：US09852808B2

公开(公告)日：2017-12-26

申请号：US14978885

申请日：2015-12-22

Applicant: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING CORPORATION

Inventor： Liang Qian

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/12 ,  G11C29/36 ,  G11C29/48 ,  G11C16/00

CPC classification number: G11C29/38 ,  G11C16/00 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/36 ,  G11C29/48

Abstract: A memory testing circuit and method are disclosed, the redesigning of a memory to be tested through incorporation therein a testing circuit includes a self-test circuit incorporating a decoder circuit, and a VPPIO I/O module incorporating an encoder circuit and having multiple functions including digital I/O, high analog voltage I/O and current I/O. An oscillator module embedded in the multiplexer circuit provides a clock signal for the testing. The VPPIO I/O module is configured to convert, by the self-test circuit, a stimulating input from a single signal pin to a parallel signal recognizable by the memory and an analog voltage/current signal, thereby accomplishing proper testing of the memory. This enables a single signal pin to test all functions of one memory, thereby increasing the number of memory dies on a wafer tested in parallel by a test instrument and reducing the testing time per wafer as well as testing cost.

公开(公告)号：US09830999B2

公开(公告)日：2017-11-28

申请号：US14716079

申请日：2015-05-19

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G11C29/12 ,  G06F9/30 ,  G06F9/38 ,  G11C29/14 ,  G11C29/32 ,  G06F15/78 ,  G11C7/06 ,  G11C16/10 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/4091

CPC classification number: G11C29/1201 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/3877 ,  G06F9/3887 ,  G06F15/785 ,  G11C7/065 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4096 ,  G11C16/10 ,  G11C29/14 ,  G11C29/32 ,  Y02D10/13

Abstract: Examples of the present disclosure provide apparatuses and methods related to performing comparison operations in a memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a first element. An example apparatus might also include a second group of memory cells coupled to a second access line and configured to store a second element. An example apparatus might also include sensing circuitry configured to compare the first element with the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations without transferring data via an input/output (I/O) line.

公开(公告)号：US20170309348A1

公开(公告)日：2017-10-26

申请号：US15138051

申请日：2016-04-25

Applicant: QUALCOMM Incorporated

Inventor： Nishi Bhushan Singh ,  Ashutosh Anand ,  Anand Bhat ,  Rajesh Tiwari ,  Shankarnarayan Bhat

IPC: G11C29/36 ,  G06F3/06 ,  G11C29/38

CPC classification number: G11C29/36 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/067 ,  G11C29/022 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/38 ,  G11C29/50012 ,  G11C2029/0401

Abstract: A method and apparatus for continuous write and read operations during memory testing. The method comprises: controlling a signal generator; triggering a write address and a data field operation each memory cycle; triggering a write signal to write to a memory each memory clock cycle; and reading a read address and a read data operation to the memory. An additional embodiment provides an apparatus for advanced memory latency testing. The apparatus includes a data generator trigger in communication with a signal generator and an address generator trigger also in communication with the signal generator.

公开(公告)号：US09786381B2

公开(公告)日：2017-10-10

申请号：US15232791

申请日：2016-08-09

Applicant: Toshiba Memory Corporation

Inventor： Yoshiki Terabayashi

IPC: G11C7/00 ,  G11C16/34 ,  G06F3/06 ,  G11C16/08 ,  G11C16/26 ,  G11C29/12

CPC classification number: G11C16/349 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C29/04 ,  G11C29/1201 ,  G11C29/4401 ,  G11C29/50004 ,  G11C2029/0409 ,  G11C2029/1204 ,  G11C2029/1208

Abstract: A semiconductor memory device includes a memory cell unit including a plurality of blocks, each of the blocks including a plurality of pages, and a circuit configured to count a number of activated or non-activated memory cells in one or more pages when a first voltage is applied to gates of memory cells of said one or more pages to read data therefrom, count a number of activated or non-activated memory cells in said one or more pages when a second voltage different from the first voltage is applied to the gates of the memory cells of said one or more pages to read data therefrom, compare the counted numbers, and store, in a register, data about deterioration of the memory cells of said one or more pages depending on a comparison result.

公开(公告)号：US09761288B2

公开(公告)日：2017-09-12

申请号：US15096578

申请日：2016-04-12

Applicant: SK hynix Inc.

Inventor： Min Chang Kim ,  Chang Hyun Kim ,  Do Yun Lee ,  Jae Jin Lee ,  Hun Sam Jung

IPC: G11C7/12 ,  G11C7/14 ,  G11C7/10

CPC classification number: G11C7/1039 ,  G11C5/025 ,  G11C5/04 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/14 ,  G11C29/022 ,  G11C29/023 ,  G11C29/12005 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/14 ,  G11C29/46 ,  G11C29/48 ,  G11C29/56012 ,  G11C2029/5602

Abstract: A memory circuit may be provided. The memory circuit may include a memory array. The memory circuit may include an input and output path circuit coupled to a probe pad and a bump pad, and may be configured to input and output a signal between an exterior of the memory circuit and the memory array. The memory circuit may include a scanning circuit configured to generate a sensing signal by sensing a signal outputted through the bump pad while performing scanning of at least one of a reference voltage and a test strobe signal.

公开(公告)号：US09741397B2

公开(公告)日：2017-08-22

申请号：US14632413

申请日：2015-02-26

Applicant: Rohm Co., Ltd.

Inventor： Kazuhisa Ukai

IPC: G11C11/24 ,  G11C5/02 ,  G11C11/412 ,  G11C29/12 ,  H01L27/02 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  G11C7/06 ,  G11C7/14 ,  G11C11/4099

CPC classification number: G11C5/025 ,  G11C7/06 ,  G11C7/14 ,  G11C11/4099 ,  G11C11/412 ,  G11C29/1201 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116

Abstract: A semiconductor memory device includes a memory array including a plurality of element blocks, the plurality of element blocks including end-portion element blocks arranged at an end portion of the memory array, and at least one dummy block disposed adjacent to the end-portion element blocks, the at least one dummy block being not in practical use. A layout pattern of the at least one dummy block is configured to correspond to only a portion of a layout pattern of the plurality of element blocks.

公开(公告)号：US09733309B2

公开(公告)日：2017-08-15

申请号：US14962626

申请日：2015-12-08

Applicant: Shanghai Huahong Grace Semiconductor Manufacturing Corporation

Inventor： Ming Li

IPC: G01R31/3185 ,  G11C29/12 ,  G11C29/16 ,  G11C29/36 ,  G11C29/48 ,  G01R31/317 ,  G11C16/00

CPC classification number: G01R31/318597 ,  G01R31/31724 ,  G01R31/318572 ,  G11C16/00 ,  G11C29/1201 ,  G11C29/16 ,  G11C29/36 ,  G11C29/48

Abstract: A built-in self-test (BIST) circuit is disclosed which integrates the functions of pins for test input data TDI, test output data TDO and an analog input signal VPP into a single digital/analog input/output module, and internally produces a test trigger signal STROBE and a digital-analog conversion signal ANA. In addition, when there is a need to power the test chip with a voltage or current, a data generation circuit of the BIST circuit can generate a digital-analog conversion signal to change an operating mode of the digital/analog input/output module and hence enable the transmission of analog data. According to the present invention, the testing can be performed with only two pins, which leads to an improvement in test efficiency and a reduction in test cost.