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公开(公告)号:US09564245B2
公开(公告)日:2017-02-07
申请号:US14141239
申请日:2013-12-26
Applicant: INTEL CORPORATION
Inventor: Bruce Querbach , Theodore Z. Schoenborn , David J. Zimmerman , David G. Ellis , Christopher W. Hampson , Ifar Wan , Yulan Zhang , Ramakrishna Mallela , William K. Lui
IPC: G06F11/263 , G06F11/27 , G11C11/406 , G11C29/00 , G11C29/36 , G11C29/44 , G11C29/10
CPC classification number: G11C29/36 , G06F11/263 , G06F11/27 , G11C11/406 , G11C29/10 , G11C29/4401 , G11C29/72 , G11C29/78 , G11C2029/4402
Abstract: In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory.
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公开(公告)号:US09922725B2
公开(公告)日:2018-03-20
申请号:US15368402
申请日:2016-12-02
Applicant: INTEL CORPORATION
Inventor: Bruce Querbach , William K. Lui , David G. Ellis , David J. Zimmerman , Theodore Z. Schoenborn , Christopher W. Hampson , Ifar Wan , Yulan Zhang
IPC: G11C29/44 , G11C29/36 , G11C29/18 , G11C29/16 , G11C29/12 , G11C29/00 , G06F11/27 , G06F11/263 , G11C29/38 , G11C29/10 , G11C29/20 , G11C11/406
CPC classification number: G11C29/38 , G06F11/263 , G06F11/27 , G11C11/406 , G11C29/10 , G11C29/1201 , G11C29/16 , G11C29/18 , G11C29/20 , G11C29/36 , G11C29/4401 , G11C29/72 , G11C29/78 , G11C29/783 , G11C2029/1202 , G11C2029/1204 , G11C2029/1206 , G11C2029/1208 , G11C2029/3602 , G11C2029/4402
Abstract: In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory. In one embodiment, data patterns are generated as a function of memory addresses and periodic address offsets.
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公开(公告)号:US09548137B2
公开(公告)日:2017-01-17
申请号:US14320164
申请日:2014-06-30
Applicant: INTEL CORPORATION
Inventor: Bruce Querbach , William K. Lui , David G. Ellis , David J. Zimmerman , Theodore Z. Schoenborn , Christopher W. Hampson , Ifar Wan , Yulan Zhang
IPC: G11C29/44 , G11C29/36 , G11C29/10 , G11C29/00 , G11C11/406 , G06F11/27 , G06F11/263
CPC classification number: G11C29/38 , G06F11/263 , G06F11/27 , G11C11/406 , G11C29/10 , G11C29/1201 , G11C29/16 , G11C29/18 , G11C29/20 , G11C29/36 , G11C29/4401 , G11C29/72 , G11C29/78 , G11C29/783 , G11C2029/1202 , G11C2029/1204 , G11C2029/1206 , G11C2029/1208 , G11C2029/3602 , G11C2029/4402
Abstract: In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory.
Abstract translation: 根据本说明书,装置包括内部缺陷检测和修复电路,其包括内置于装置内的自检逻辑电路和内置在装置内的自修复逻辑电路。 在一个实施例中,内置自检逻辑电路可以被配置为自动识别存储器中的有缺陷的存储器单元。 在识别一个或多个有缺陷的存储器单元时,内置的自修复逻辑电路可以被配置为通过用存储器内的备用单元替换有缺陷的单元来自动修复有缺陷的存储器单元。