公开(公告)号：US11961546B2

公开(公告)日：2024-04-16

申请号：US17391639

申请日：2021-08-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Fu Lee ,  Hon-Jarn Lin ,  Po-Hao Lee ,  Ku-Feng Lin ,  Yi-Chun Shih ,  Yu-Der Chih

IPC: G11C11/06 ,  G11C11/08 ,  G11C11/16 ,  H10B61/00 ,  H10N50/10

CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  H10B61/22 ,  H10N50/10

Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.

公开(公告)号：US11943936B2

公开(公告)日：2024-03-26

申请号：US17400615

申请日：2021-08-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Yu-Der Chih ,  May-Be Chen ,  Yun-Sheng Chen ,  Jonathan Tsung-Yung Chang ,  Wen Zhang Lin ,  Chrong Jung Lin ,  Ya-Chin King ,  Chieh Lee ,  Wang-Yi Lee

IPC: H10B63/00 ,  H01L29/40 ,  H01L29/78

CPC classification number: H10B63/30 ,  H01L29/401 ,  H01L29/785

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first transistor, a first resistive random access memory (RRAM) resistor, and a second RRAM resistor. The first resistor includes a first resistive material layer, a first electrode shared by the second resistor, and a second electrode. The second resistor includes the first electrode, a second resistive material layer, and a third electrode. The first electrode is electrically coupled to the first transistor.

公开(公告)号：US11923036B2

公开(公告)日：2024-03-05

申请号：US18168226

申请日：2023-02-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Chun Shih ,  Chia-Fu Lee ,  Yu-Der Chih

IPC: G11C7/08 ,  G11C7/06 ,  G11C7/10 ,  G11C11/16 ,  G11C29/42

CPC classification number: G11C7/08 ,  G11C7/067 ,  G11C7/1039 ,  G11C11/1673 ,  G11C29/42

Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.

公开(公告)号：US11783870B2

公开(公告)日：2023-10-10

申请号：US17843786

申请日：2022-06-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Fu Lee ,  Hon-Jarn Lin ,  Yu-Der Chih

IPC: G11C7/02 ,  G11C7/06

CPC classification number: G11C7/062 ,  G11C2207/063

Abstract: A sense amplifier is provided. A first terminal of a first invertor is connected to a power node and a second terminal of the first invertor is connected to a cell current source. A first terminal of a second invertor is connected to the power node and a second terminal of the second invertor is connected to a reference current source. The first invertor is cross coupled with the second invertor at a first node and a second node. A pre-charge circuit is connected to the first node and the second node. A first pull up transistor and a second pull up transistor are connected between a supply voltage node and the power node. A signal level detector circuit is connected to the second pull up transistor. The signal level detector circuit switches on the second pull up transistor when a remaining voltage on one of the first node and the second node is below a reference voltage.

公开(公告)号：US20230273752A1

公开(公告)日：2023-08-31

申请号：US18313374

申请日：2023-05-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hiroki Noguchi ,  Shih-Lien Linus Lu ,  Yu-Der Chih ,  Yih Wang

IPC: G06F3/06 ,  G06F9/48 ,  G06F1/28

CPC classification number: G06F3/0659 ,  G06F1/28 ,  G06F3/0604 ,  G06F3/0673 ,  G06F9/4893

Abstract: A memory device including a memory array with a plurality of memory macros, a power supplying circuit, and a controller is provided. The power supplying circuit is coupled to the memory array. The controller is coupled to the memory array. The power supplying circuit is configured to provide power to perform write operations to a number of the memory macros at the same time. The number of the memory macros for the write operations performed at the same time is not higher than a maximum number of the memory macros. The controller obtains the maximum number of the memory macros for the write operations performed at the same time by the power supplying circuit. The controller re-arranges a schedule for a sequence of the write operations of the memory macros to generate a re-arranged schedule. The maximum number is taken as a threshold value. In the re-arranged schedule, a number of part of the memory macros for the write operations performed at the same time is equal to or less then the threshold value.

公开(公告)号：US11714717B2

公开(公告)日：2023-08-01

申请号：US17703857

申请日：2022-03-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Der Chih ,  Chia-Fu Lee ,  Chien-Yin Liu ,  Yi-Chun Shih ,  Kuan-Chun Chen ,  Hsueh-Chih Yang ,  Shih-Lien Linus Lu

IPC: G06F11/10 ,  H03M13/29 ,  H03M13/15 ,  H03M13/19 ,  G11C29/42

CPC classification number: G06F11/1076 ,  G06F11/1012 ,  G06F11/1048 ,  H03M13/2906 ,  H03M13/2909 ,  H03M13/2927 ,  G11C29/42 ,  H03M13/152 ,  H03M13/1515 ,  H03M13/19

Abstract: A method of screening weak bits in a memory array includes dividing the memory array into a first and a second memory array, storing a first set of data in the first memory array, performing a first baking process on the first memory array or applying a first magnetic field to the first memory array, determining that a first portion of the first set of data stored in the first memory array is altered by the first baking process or the first magnetic field, and at least one of replacing memory cells of a first set of memory cells that are storing the first portion of the first set of data with corresponding memory cells in the second memory array of the memory array, or not using the memory cells of the first set of memory cells storing the first portion of the first set of data.

公开(公告)号：US11688436B2

公开(公告)日：2023-06-27

申请号：US17829333

申请日：2022-05-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ku-Feng Lin ,  Yu-Der Chih

IPC: G11C7/02 ,  G11C7/06 ,  G11C7/08 ,  G11C7/12

CPC classification number: G11C7/062 ,  G11C7/08 ,  G11C7/12

Abstract: A sense amplifier includes a voltage comparator with offset compensation, a first clamping device and a second clamping device. The voltage comparator is coupled to a bit line and a reference bit line respectively, and configured to compare a first input voltage and a second input voltage to output a sensing signal. The first clamping circuit and the second clamping circuit trim a voltage corresponding to the bit line and a voltage corresponding to the reference bit line respectively to match the voltage corresponding to the reference bit line with the voltage corresponding to the bit line.

公开(公告)号：US11651826B2

公开(公告)日：2023-05-16

申请号：US17693908

申请日：2022-03-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Der Chih

IPC: G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C17/08 ,  G11C7/06 ,  G11C7/10 ,  G11C16/04

CPC classification number: G11C16/24 ,  G11C7/06 ,  G11C7/1063 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/26 ,  G11C17/08

Abstract: A memory device is provided. The memory device includes a first transistor and a second transistor connected in series with the first transistor. The second transistor is programmable between a first state and a second state. A bit line connected to the second transistor. A sense amplifier connected to the bit line. The sense amplifier is operative to sense data from the bit line. A feedback circuit connected to the sense amplifier, wherein the feedback circuit is operative to control a bit line current of the bit-line.

公开(公告)号：US20230121502A1

公开(公告)日：2023-04-20

申请号：US18064098

申请日：2022-12-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Lien Linus Lu ,  Kun-hsi Li ,  Shih-Liang Wang ,  Jonathan Tsung-Yung Chang ,  Yu-Der Chih ,  Cheng-En Lee

IPC: H04L9/08 ,  G06F7/58 ,  H04L9/32

Abstract: Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) device. The PUF can include a random number generator that can create random bits. The random bits may be stored in a nonvolatile memory. The number of random bits stored in the nonvolatile memory allows for a plurality of challenge and response interactions to obtain a plurality of security keys from the PUF.

公开(公告)号：US11621040B2

公开(公告)日：2023-04-04

申请号：US17365732

申请日：2021-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Der Chih ,  Meng-Fan Chang ,  May-Be Chen ,  Cheng-Xin Xue ,  Je-Syu Liu

IPC: G11C8/00 ,  G11C13/00 ,  G11C7/10 ,  G06F7/544 ,  G11C7/06

Abstract: A system includes a global generator and local generators. The global generator is coupled to a memory array, and is configured to generate global signals, according to a number of a computational output of the memory array. The local generators are coupled to the global generator and the memory array, and are configured to generate local signals, according to the global signals. Each one of the local generators includes a first reference circuit and a local current mirror. The first reference circuit is coupled to the global generator, and is configured to generate a first reference signal at a node, in response to a first global signal of the global signals. The local current mirror is coupled to the first reference circuit at the node, and is configured to generate the local signals, by mirroring a summation of at least one signal at the node.