公开(公告)号：US20190157205A1

公开(公告)日：2019-05-23

申请号：US16254126

申请日：2019-01-22

Applicant: INTEL CORPORATION

Inventor： Nitin A. Deshpande ,  Omkar G. Karhade

IPC: H01L23/538 ,  H01L23/13 ,  H01L23/522 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/5383 ,  H01L21/486 ,  H01L23/13 ,  H01L23/522 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/14 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15153 ,  H01L2924/15192

Abstract: A microelectronic structure includes a substrate having a first surface and a cavity extending into the substrate from the substrate first surface, a first microelectronic device and a second microelectronic device attached to the substrate first surface, and a bridge disposed within the substrate cavity and attached to the first microelectronic device and to the second microelectronic device. The bridge includes a plurality conductive vias extending from a first surface to an opposing second surface of the bridge, wherein the conductive vias are electrically coupled to deliver electrical signals from the substrate to the first microelectronic device and the second microelectronic device. The bridge further creates at least one electrical signal connection between the first microelectronic device and the second microelectronic device.

公开(公告)号：US10229882B2

公开(公告)日：2019-03-12

申请号：US15668179

申请日：2017-08-03

Applicant: INTEL CORPORATION

Inventor： Nitin A. Deshpande ,  Omkar G. Karhade

IPC: H01L23/538 ,  H01L23/13 ,  H01L23/522 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A microelectronic structure includes a substrate having a first surface and a cavity extending into the substrate from the substrate first surface, a first microelectronic device and a second microelectronic device attached to the substrate first surface, and a bridge disposed within the substrate cavity and attached to the first microelectronic device and to the second microelectronic device. The bridge includes a plurality conductive vias extending from a first surface to an opposing second surface of the bridge, wherein the conductive vias are electrically coupled to deliver electrical signals from the substrate to the first microelectronic device and the second microelectronic device. The bridge further creates at least one electrical signal connection between the first microelectronic device and the second microelectronic device.

公开(公告)号：US09275955B2

公开(公告)日：2016-03-01

申请号：US14132774

申请日：2013-12-18

Applicant: INTEL CORPORATION

Inventor： Ravindranath V. Mahajan ,  Christopher J. Nelson ,  Omkar G. Karhade ,  Feras Eid ,  Nitin A. Deshpande ,  Shawna M. Liff

IPC: H01L23/28 ,  H01L23/538 ,  H01L25/00 ,  H01L25/16 ,  H01L23/00 ,  H01L23/367 ,  H01L23/14 ,  H01L23/31 ,  H01L23/433 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L23/5381 ,  H01L21/563 ,  H01L21/568 ,  H01L23/145 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/24 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/165 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/17181 ,  H01L2224/24145 ,  H01L2224/24245 ,  H01L2224/291 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29116 ,  H01L2224/2912 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92124 ,  H01L2224/92224 ,  H01L2224/92242 ,  H01L2224/92244 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/12042 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/0665

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及具有分别具有第一和第二输入/输出（I / O）互连结构的第一和第二裸片的集成电路（IC）封装。 IC封装可以包括具有分别耦合到第一和第二I / O互连结构的一部分的第一和第二电路由特征的桥。 在实施例中，第一和第二电路由特征可以设置在桥的一侧; 并且第三电路布线特征可以设置在相对侧上。 第一和第二电路由特征可以被配置为在第一管芯和第二管芯之间路由电信号，并且第三电路由特征可以被配置为在一侧和相对侧之间路由电信号。 第一管芯，第二管芯和桥可以嵌入电绝缘材料中。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20150163904A1

公开(公告)日：2015-06-11

申请号：US14102757

申请日：2013-12-11

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  John S. Guzek ,  Johanna M. Swan ,  Christopher J. Nelson ,  Nitin A. Deshpande ,  William J. Lambert ,  Charles A. Gealer ,  Feras Eid ,  Islam A. Salama ,  Kemal Aygun ,  Sasha N. Oster ,  Tyler N. Osborn

IPC: H05K1/11 ,  H05K1/18 ,  H05K3/40 ,  G06F1/18

CPC classification number: H01L25/16 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/50 ,  H01L24/86 ,  H01L25/00 ,  H01L25/0655 ,  H01L2224/0405 ,  H01L2224/04105 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/29078 ,  H01L2224/86203 ,  H01L2224/86815 ,  H05K1/185 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction. An interconnect comprising an interconnect substrate having a plurality of electrically isolated conductive traces extending in the x-direction on a first surface of the interconnect substrate may be attached to the at least one first microelectronic device connection structure row and the at least one second microelectronic device connection structure row, such that at least one interconnect conductive trace forms a connection between a first microelectronic device connection structure and its corresponding second microelectronic device connection structure.

Abstract translation: 本说明书的微电子封装可以包括具有与其电连接的至少一行连接结构的第一微电子器件和具有与其电连接的至少一排连接结构的第二微电子器件，其中所述至少一个 第一微电子器件行与X方向上的至少一个第二微电子器件行内的对应连接结构对准。 包括具有在互连衬底的第一表面上沿x方向延伸的多个电隔离导电迹线的互连衬底的互连可以附接到所述至少一个第一微电子器件连接结构行和所述至少一个第二微电子器件 连接结构行，使得至少一个互连导电迹线形成第一微电子器件连接结构与其对应的第二微电子器件连接结构之间的连接。

公开(公告)号：US20250062278A1

公开(公告)日：2025-02-20

申请号：US18452152

申请日：2023-08-18

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Debendra Mallik ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Nitin A. Deshpande ,  Ravindranath Vithal Mahajan ,  Abhishek A. Sharma ,  Joshua Fryman ,  Stephen Morein ,  Matthew Adiletta ,  Michael Crocker ,  Aaron Gorius

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522

Abstract: Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including a conductive trace that is parallel to the first and second surfaces, and the conductive trace is exposed at the third surface; and a second IC die including a fourth surface, wherein the fourth surface of the second IC die is electrically coupled to the third surface of the first IC die by an interconnect including solder.

公开(公告)号：US12181710B2

公开(公告)日：2024-12-31

申请号：US17237375

申请日：2021-04-22

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Xiaoqian Li ,  Tarek A. Ibrahim ,  Ravindranath Vithal Mahajan ,  Nitin A. Deshpande

IPC: G02B6/122 ,  G02B6/12

Abstract: Photonic packages and device assemblies that include photonic integrated circuits (PICs) coupled to optical lenses on lateral sides of the PICs. An example photonic package comprises a package support, an integrated circuit (IC), an insulating material, a PIC having an active side and a lateral side substantially perpendicular to the active side. At least one optical structure is on the active side. A substantial portion of the active side is in contact with the insulating material, and the PIC is electrically coupled to the package support and to the IC. The photonic package further includes an optical lens coupled to the PIC on the lateral side. In some embodiments, the photonic package further includes an interposer between the PIC or the IC and the package support.

公开(公告)号：US20240319437A1

公开(公告)日：2024-09-26

申请号：US18189844

申请日：2023-03-24

Applicant: Intel Corporation

Inventor： Xiaoqian Li ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Julia Chiu ,  Chia-Pin Chiu ,  Kaveh Hosseini ,  Madhubanti Chatterjee

IPC: G02B6/12 ,  G02B6/136

CPC classification number: G02B6/12002 ,  G02B6/136

Abstract: A photonic integrated circuit (PIC), a semiconductor assembly including the PIC, a multi-chip package including the PIC, and a method of forming the PIC. The PIC includes a PIC substrate, and a semiconductor layer on a top surface of the PIC substrate and including a semiconductor material and an optical component. The PIC substrate defines an air cavity therein extending in a direction from a bottom surface of the PIC substrate toward and in registration with the optical component. The semiconductor layer is free of any opening therethrough in communication with the air cavity.

公开(公告)号：US20230420436A1

公开(公告)日：2023-12-28

申请号：US17846109

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Omkar G. Karhade ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Nitin A. Deshpande

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/522 ,  H01L23/48 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L24/08 ,  H01L23/5226 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/08145

Abstract: Embodiments of an integrated circuit (IC) die comprise: a first region having a first surface; a second region attached to the first region along a first planar interface that is orthogonal to the first surface; and a third region attached to the second region along a second planar interface that is parallel to the first planar interface, the third region having a second surface, the second surface being coplanar with the first surface. The first region and the third region comprise a plurality of layers of conductive traces in a dielectric material, the conductive traces being orthogonal to the first and second surfaces; and bond-pads on the first and second surfaces, the bond-pads comprising portions of the respective conductive traces exposed on the first and second surfaces.

公开(公告)号：US11804441B2

公开(公告)日：2023-10-31

申请号：US16902910

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Mohit Bhatia ,  Debendra Mallik

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L25/18

CPC classification number: H01L23/5385 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/73253

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate including a first metal layer and a second metal layer; a cavity in the substrate, wherein a portion of the first metal layer in the substrate and a portion of the second metal layer in the substrate are exposed in the cavity; and a bridge component in the cavity, the bridge component includes a first conductive contact at a first face and a second conductive contacts at an opposing second face, wherein the second face of the bridge component is between the first face of the bridge component and a bottom surface of the cavity in the substrate, and wherein the second conductive contact is electrically coupled to the portion of the first metal layer in the cavity.

公开(公告)号：US20230343769A1

公开(公告)日：2023-10-26

申请号：US17728147

申请日：2022-04-25

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Debendra Mallik ,  Steve Cho ,  Babak Sabi

IPC: H01L25/00 ,  H01L21/78 ,  H01L23/00 ,  H01L23/522 ,  H01L25/18

CPC classification number: H01L25/18 ,  H01L21/78 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/13 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155

Abstract: Embodiments of a microelectronic assembly comprise a microelectronic assembly, comprising: a stack of layers coupled by at least fusion bonds; a package substrate coupled to a first layer in the stack of layers; one or more dies in the first layer; and one or more dies in a second layer in the stack of layers, the second layer coupled to the first layer, wherein: a copper lining is between adjacent surfaces of any two adjacent dies in at least one of the first layer and the second layer, and the copper lining contacts and substantially covers the adjacent surfaces. In various embodiments, the dies comprise dummy dies and integrated circuit (IC) dies, the dummy dies are one of: semiconductor dies without any ICs, and semiconductor dies having non-functional ICs, and the IC dies comprise semiconductor dies having functional ICs.