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49 条记录 (耗时 0.028 秒)

    Semiconductor integrated circuit comprised of pass-transistor circuits with different mutual connections
    45.
    发明授权
    Semiconductor integrated circuit comprised of pass-transistor circuits with different mutual connections 失效
    半导体集成电路由具有不同相互连接的通过晶体管电路组成

    公开(公告)号：US5923189A

    公开(公告)日：1999-07-13

    申请号：US633053

    申请日：1996-04-16

    申请人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

    发明人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

    IPC分类号： G06F17/50 ,  H03K19/173 ,  H03K19/0948

    CPC分类号： H03K19/1736 ,  G06F17/505 ,  H03K19/1737

    摘要： For the relation between the first and second pass-transistor circuits (PT1, PT2), the output signal of the preceding-stage is supplied to the gate of the succeeding-stage, and for the relation between the second and third pass-transistor circuits (PT2, PT3), the output signal of the preceding-stage is supplied to the source-drain path of the succeeding-stage. The first pass-transistor circuit (PT1) receives on its first input node (In1) and second input node (In2) the first input signal and the second input signal that are logically independent from each other. This logic circuit requires a smaller number of transistors and is capable of reducing the power consumption and delay and accomplishing an intricate logic function.

    摘要翻译： 对于第一和第二通过晶体管电路（PT1，PT2）之间的关系，前级的输出信号被提供给后级的栅极，并且对于第二和第三通过晶体管电路之间的关系 （PT2，PT3），将前级的输出信号提供给后级的源极 - 漏极路径。 第一通过晶体管电路（PT1）在第一输入节点（In1）和第二输入节点（In2）上接收逻辑上彼此独立的第一输入信号和第二输入信号。 该逻辑电路需要较少数量的晶体管，并且能够降低功耗并延迟并完成复杂的逻辑功能。

    Nonvolatile semiconductor memory device
    46.
    发明授权
    Nonvolatile semiconductor memory device 失效

    公开(公告)号：US5917752A

    公开(公告)日：1999-06-29

    申请号：US457761

    申请日：1995-06-01

    申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    IPC分类号： G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  G11C11/34

    CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

    摘要： Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.

    Sense amplifier, SRAM, and microprocessor
    47.
    发明授权
    Sense amplifier, SRAM, and microprocessor 失效
    感应放大器，SRAM和微处理器

    公开(公告)号：US5534800A

    公开(公告)日：1996-07-09

    申请号：US133218

    申请日：1993-10-07

    申请人： Mitsuru Hiraki ,  Yasuhiko Sasaki ,  Koichi Seki ,  Tatsuji Matsuura

    发明人： Mitsuru Hiraki ,  Yasuhiko Sasaki ,  Koichi Seki ,  Tatsuji Matsuura

    IPC分类号： G11C11/419 ,  G11C7/00

    CPC分类号： G11C11/419

    摘要： A sense amplifier for an SRAM providing both a small power consumption and a high speed sensing operation. The sense amplifier includes a first p-channel MOSFET having a source terminal connected to a bit line, a second p-channel MOSFET having a source terminal connected to another bit line, a first n-channel MOSFET having a drain terminal connected to a drain terminal of the first p-channel MOSFET and a gate terminal connected to a drain terminal of the second p-channel MOSFET and to a gate terminal of the first p-channel MOSFET, a second n-channel MOSFET having a drain terminal connected to a drain terminal of the second p-channel MOSFET, a gate terminal connected to a drain terminal of the first p-channel MOSFET and to a gate terminal of the second p-channel MOSFET, and a source terminal connected to a source terminal of the first n-channel MOSFET, a third p-channel MOSFET for controlling the connection/disconnection between a first power source (Vcc) and the drain terminal of the first p-channel MOSFET, a fourth p-channel MOSFET for controlling the connection/disconnection between the first power source Vcc and the drain terminal of the second p-channel MOSFET, and a third n-channel MOSFET for controlling the connection/disconnection between a second power source (ground) and the source terminals of the second n-channel MOSFETs.

    摘要翻译： 一种用于SRAM的读出放大器，既提供小功率消耗又提供高速感测操作。 读出放大器包括具有连接到位线的源极端子的第一p沟道MOSFET，具有连接到另一个位线的源极端子的第二p沟道MOSFET，具有连接到漏极的漏极端子的第一n沟道MOSFET 第一p沟道MOSFET的端子和连接到第二p沟道MOSFET的漏极端子和栅极端子的栅极端子连接到第一p沟道MOSFET的栅极端子，第二n沟道MOSFET，其漏极端子连接到 第二p沟道MOSFET的漏极端子，连接到第一p沟道MOSFET的漏极端子的栅极端子和与第二p沟道MOSFET的栅极端子连接的栅极端子以及连接到第一p沟道MOSFET的源极端子的源极端子 n沟道MOSFET，用于控制第一电源（Vcc）和第一p沟道MOSFET的漏极端子之间的连接/断开的第三p沟道MOSFET，用于控制第一p沟道MOSFET之间的连接/断开的第四p沟道MOSFET f 第一电源Vcc和第二p沟道MOSFET的漏极端子，以及用于控制第二电源（地）和第二n沟道MOSFET的源极端子之间的连接/断开的第三n沟道MOSFET。

    Semiconductor device
    48.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US5359221A

    公开(公告)日：1994-10-25

    申请号：US86096

    申请日：1993-07-06

    申请人： Masafumi Miyamoto ,  Ryo Nagai ,  Tatsuya Ishii ,  Koichi Seki

    发明人： Masafumi Miyamoto ,  Ryo Nagai ,  Tatsuya Ishii ,  Koichi Seki

    IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

    CPC分类号： H01L29/7833 ,  H01L21/26586 ,  H01L21/823807 ,  H01L29/1083 ,  H01L29/66575 ,  H01L29/66621 ,  H01L29/66659

    摘要： Source and drain regions are formed in first regions of low concentration formed on a surface of a semiconductor surface, and a second region with doping concentration higher than that of the first regions is formed around the first regions. Further in the second region, third regions with doping concentration higher than that of the second region are formed separate from each other. By virtue of this, a rise of the threshold voltage attendant on a decrease of the channel length is canceled out by the third regions and the short channel effect is suppressed. Further, since doping concentration of the first region is low, high carrier mobility can be obtained.

    摘要翻译： 源极和漏极区域形成在半导体表面的表面上形成的低浓度的第一区域中，并且在第一区域周围形成掺杂浓度高于第一区域的第二区域。 此外，在第二区域中，掺杂浓度高于第二区域的第三区域形成为彼此分离。 由此，通过第三区域抵消伴随着沟道长度的减小的阈值电压的上升，抑制短路效应。 此外，由于第一区域的掺杂浓度低，因此可以获得高载流子迁移率。