公开(公告)号：US20240312977A1

公开(公告)日：2024-09-19

申请号：US18668639

申请日：2024-05-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA ,  Roberto SIMOLA

IPC: H01L27/01 ,  H01L21/70 ,  H10B41/41 ,  H10B41/42

CPC classification number: H01L27/016 ,  H01L21/707 ,  H10B41/41 ,  H10B41/42

Abstract: An integrated circuit includes a semiconductor substrate, a conductive layer above a front face of the substrate, a first metal track in a first metal level, and a pre-metal dielectric region located between the conductive layer and the first metal level. A metal-insulator-metal-type capacitive structure is located in a trench within the pre-metal dielectric region. The capacitive structure includes a first metal layer electrically connected with the conductive layer, a second metal layer electrically connected with the first metal track, and a dielectric layer between the first metal layer and the second metal layer.

公开(公告)号：US12096629B2

公开(公告)日：2024-09-17

申请号：US18344161

申请日：2023-06-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Ling Shih ,  Yong-Shiuan Tsair

IPC: H01L29/423 ,  G11C29/14 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/522 ,  H01L23/528 ,  H01L29/08 ,  H01L29/66 ,  H01L29/788 ,  H10B41/30 ,  H10B41/42

CPC classification number: H10B41/42 ,  G11C29/14 ,  H01L21/31116 ,  H01L21/32137 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/0847 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788 ,  H10B41/30 ,  H01L29/66545

Abstract: Various embodiments of the present application are directed to a method for forming an integrated circuit (IC) comprising forming a multilayer film to form a plurality of memory cell structures disposed over a substrate and a plurality of memory test structures next to the memory cell structures. A memory test structure comprises a dummy control gate separated from the substrate by a dummy floating gate. The method further comprises forming a conductive floating gate test contact via along sidewalls of the dummy control gate and the dummy floating gate.

公开(公告)号：US11968830B2

公开(公告)日：2024-04-23

申请号：US18178527

申请日：2023-03-05

Applicant: Winbond Electronics Corp.

Inventor： Chung-Hsuan Wang

IPC: H01L21/00 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H10B41/30 ,  H10B41/42

CPC classification number: H10B41/42 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/30

Abstract: Provided is a method of manufacturing a memory device and a patterning method. The patterning method includes following steps. A control structure including stop layers and oxide layers stacked alternately, a hard mask layer, and a mask pattern are sequentially formed on a target layer. A photoresist layer is formed in the mask pattern on the hard mask layer. A portion of the hard mask layer and a portion of the control structure are removed to form first openings by using the photoresist layer and the mask pattern as a mask. The photoresist layer and the hard mask layer are removed to form a second opening having a bottom surface higher than that of the first openings. At least one etching process is performed so that the first and second openings extend into and divide the control structure and the target layer into stack structures.

公开(公告)号：US11968829B2

公开(公告)日：2024-04-23

申请号：US17834746

申请日：2022-06-07

Applicant: Silicon Storage Technology, Inc.

Inventor： Zhuoqiang Jia ,  Leo Xing ,  Xian Liu ,  Serguei Jourba ,  Nhan Do

IPC: H10B41/42 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

CPC classification number: H10B41/42 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

Abstract: A method includes recessing an upper surface of a substrate in first and second areas relative to a third area, forming a first conductive layer in the first area, forming a second conductive layer in the three areas, selectively removing the first and second conductive layers in the first area, while maintaining the second conductive layer in the second and third areas, leaving pairs of stack structures in the first area respectively having a control gate of the second conductive layer and a floating gate of the first conductive layer, forming a third conductive layer in the three areas, recessing the upper surface of the third conductive layer below tops of the stack structures and removing the third conductive layer from the second and third areas, removing the second conductive layer from the second and third areas, and forming blocks of metal material in the second and third areas.

公开(公告)号：US20240032293A1

公开(公告)日：2024-01-25

申请号：US18374497

申请日：2023-09-28

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Mei Lan Guo ,  Yushi Hu ,  Ji Xia ,  Hongbin Zhu

IPC: H10B41/42 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B41/42 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: In certain aspects, a semiconductor device includes a substrate, a stack structure over the substrate and including interleaved conductive layers and dielectric layers, and a connection structure extending through the stack structure into the substrate. The connection structure includes a conductor layer and a spacer over a sidewall of the conductor layer. The conductor layer of the connection structure is in direct contact with the substrate.

公开(公告)号：US20240032292A1

公开(公告)日：2024-01-25

申请号：US18081161

申请日：2022-12-14

Applicant: SK hynix Inc.

Inventor： Jae Taek KIM

IPC: H10B41/35 ,  H10B41/41 ,  H10B41/20 ,  H10B41/42 ,  H10B43/20 ,  H10B43/35 ,  H10B43/40 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L21/3105

CPC classification number: H10B41/35 ,  H10B41/41 ,  H10B41/20 ,  H10B41/42 ,  H10B43/20 ,  H10B43/35 ,  H10B43/40 ,  H01L29/1033 ,  H01L29/0649 ,  H01L29/0847 ,  H01L21/31053 ,  H10B99/22

Abstract: A semiconductor memory device includes: a substrate; a source stack structure and a source insulating layer disposed over the substrate to be spaced apart from each other; an isolation insulating layer disposed between the source stack structure and the source insulating layer; a first stack structure disposed over the source stack structure; a second stack structure disposed over the source insulating layer; a vertical structure penetrating the first stack structure and a portion of the source stack structure; and a lower contact penetrating the source insulating layer.

公开(公告)号：US11785769B2

公开(公告)日：2023-10-10

申请号：US17857034

申请日：2022-07-03

Applicant: Winbond Electronics Corp.

Inventor： Hsin-Huang Shen ,  Yu-Shu Cheng ,  Yao-Ting Tsai

IPC: H01L29/66 ,  H10B41/30 ,  H01L29/06 ,  H01L29/423 ,  H01L29/788 ,  H01L21/762 ,  H01L21/28 ,  H01L29/78 ,  H10B41/42 ,  H01L21/3213

CPC classification number: H10B41/30 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66545 ,  H01L29/66598 ,  H01L29/66825 ,  H01L29/7833 ,  H01L29/7883 ,  H10B41/42 ,  H01L21/3213

Abstract: A manufacturing method of semiconductor device is provided. In the manufacturing method, a tunneling dielectric layer, floating gates on the tunneling dielectric layer, an ONO layer on the floating gates, and control gates on the ONO layer are formed. During the formation of the floating gates and the control gates, reactive-ion etching (R.I.E.) is not used at all, and thus damage to the floating and control gates from high-density plasma is prevented, such as charge trap in the floating gates may be significantly reduced to improve the reliability of data storage.

公开(公告)号：US11758721B2

公开(公告)日：2023-09-12

申请号：US17202193

申请日：2021-03-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei Cheng Wu ,  Li-Feng Teng

IPC: H10B41/42 ,  H01L29/66 ,  H01L21/28 ,  H10B41/00 ,  H10B41/20 ,  H10B41/30 ,  H10B41/40 ,  H10B41/44 ,  H10B41/46 ,  H10B41/50 ,  H10B69/00 ,  H01L29/423

CPC classification number: H10B41/42 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66545 ,  H01L29/66825 ,  H10B41/00 ,  H10B41/20 ,  H10B41/30 ,  H10B41/40 ,  H10B41/44 ,  H10B41/46 ,  H10B41/50 ,  H10B69/00

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate. A second dielectric layer is disposed between the floating gate and the control gate, having one of a silicon nitride layer, a silicon oxide layer and multilayers thereof. A third dielectric layer is disposed between the second dielectric layer and the control gate, and includes a dielectric material having a dielectric constant higher than silicon nitride.

公开(公告)号：US11729970B2

公开(公告)日：2023-08-15

申请号：US17121555

申请日：2020-12-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: H01L27/11531 ,  G06N3/08 ,  G11C16/04 ,  H01L29/788 ,  H10B41/42

CPC classification number: H10B41/42 ,  G06N3/08 ,  G11C16/0425 ,  H01L29/7883

Abstract: Numerous embodiments for reading a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one embodiment, an input comprises a set of input bits that result in a series of input pulses applied to a terminal of the selected memory cell, further resulting in a series of output signals that are summed to determine the value stored in the selected memory cell. In another embodiment, an input comprises a set of input bits, where each input bit results in a single pulse or no pulse being applied to a terminal of the selected memory cell, further resulting in a series of output signals which are then weighted according to the binary bit location of the input bit, and where the weighted signals are then summed to determine the value stored in the selected memory cell.

公开(公告)号：US20240365542A1

公开(公告)日：2024-10-31

申请号：US18764868

申请日：2024-07-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wei-Cheng WU ,  Li-Feng TENG

IPC: H10B41/42 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H10B41/30 ,  H10B41/35 ,  H10B41/44 ,  H10B41/47 ,  H10B41/48 ,  H10B43/30

CPC classification number: H10B41/42 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66545 ,  H10B41/30 ,  H10B41/35 ,  H10B41/44 ,  H10B41/47 ,  H10B41/48 ,  H10B43/30

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer, and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.