公开(公告)号：US11631685B2

公开(公告)日：2023-04-18

申请号：US17412291

申请日：2021-08-26

Applicant: Winbond Electronics Corp.

Inventor： Chung-Hsuan Wang

IPC: H01L21/00 ,  H01L27/11531 ,  H01L27/11521 ,  H01L29/66 ,  H01L29/788 ,  H01L21/28 ,  H01L29/423

Abstract: Provided is a memory device including a substrate, a plurality of first stack structures, and a plurality of second stack structures. The substrate includes an array region and a periphery region. The first stack structures are disposed on the substrate in the array region. Each first stack structure sequentially includes: a first tunneling dielectric layer, a first floating gate, a first inter-gate dielectric layer, a first control gate, a first metal layer, a first cap layer, and the first stop layer. The second stack structures are disposed on the substrate in the periphery region. Each second stack structure sequentially includes: a second tunneling dielectric layer, a second floating gate, a second inter-gate dielectric layer, a second control gate, a second metal layer, a second cap layer, and the second stop layer. The first stack structures have a pattern density greater than a pattern density of the second stack structures.

公开(公告)号：US20230209823A1

公开(公告)日：2023-06-29

申请号：US18178527

申请日：2023-03-05

Applicant: Winbond Electronics Corp.

Inventor： Chung-Hsuan Wang

IPC: H10B41/42 ,  H01L29/66 ,  H01L29/788 ,  H01L21/28 ,  H01L29/423 ,  H10B41/30

CPC classification number: H10B41/42 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/40114 ,  H01L29/42328 ,  H10B41/30

Abstract: Provided is a method of manufacturing a memory device and a patterning method. The patterning method includes following steps. A control structure including stop layers and oxide layers stacked alternately, a hard mask layer, and a mask pattern are sequentially formed on a target layer. A photoresist layer is formed in the mask pattern on the hard mask layer. A portion of the hard mask layer and a portion of the control structure are removed to form first openings by using the photoresist layer and the mask pattern as a mask. The photoresist layer and the hard mask layer are removed to form a second opening having a bottom surface higher than that of the first openings. At least one etching process is performed so that the first and second openings extend into and divide the control structure and the target layer into stack structures.

公开(公告)号：US20210193918A1

公开(公告)日：2021-06-24

申请号：US17109147

申请日：2020-12-02

Applicant: Winbond Electronics Corp.

Inventor： Chung-Hsuan Wang ,  Yu-Ting Chen ,  Tz-Hau Guo ,  Chang-Hsuan Wu ,  Chiung-Lin Hsu

IPC: H01L45/00 ,  H01L27/24

Abstract: Provided are a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes first, second, and third electrodes, a variable resistance layer, a selection layer, and first and second bit lines. The second electrode and the third electrode are on the first electrode. The second and third electrodes are separated from each other and overlapped with the sidewall and the top surface of the first electrode. The variable resistance layer is between the first and second electrodes and between the first and third electrodes. The selection layer is between the variable resistance layer and the first electrode. The first bit line is on the second electrode and electrically connected to the second electrode via a first contact.
The second bit line is on the third electrode and electrically connected to the third electrode via a second contact.

公开(公告)号：US11968830B2

公开(公告)日：2024-04-23

申请号：US18178527

申请日：2023-03-05

Applicant: Winbond Electronics Corp.

Inventor： Chung-Hsuan Wang

IPC: H01L21/00 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H10B41/30 ,  H10B41/42

CPC classification number: H10B41/42 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/30

Abstract: Provided is a method of manufacturing a memory device and a patterning method. The patterning method includes following steps. A control structure including stop layers and oxide layers stacked alternately, a hard mask layer, and a mask pattern are sequentially formed on a target layer. A photoresist layer is formed in the mask pattern on the hard mask layer. A portion of the hard mask layer and a portion of the control structure are removed to form first openings by using the photoresist layer and the mask pattern as a mask. The photoresist layer and the hard mask layer are removed to form a second opening having a bottom surface higher than that of the first openings. At least one etching process is performed so that the first and second openings extend into and divide the control structure and the target layer into stack structures.

公开(公告)号：US20220320126A1

公开(公告)日：2022-10-06

申请号：US17412291

申请日：2021-08-26

Applicant: Winbond Electronics Corp.

Inventor： Chung-Hsuan Wang

IPC: H01L27/11531 ,  H01L27/11521 ,  H01L29/423 ,  H01L29/788 ,  H01L21/28 ,  H01L29/66

Abstract: Provided is a memory device including a substrate, a plurality of first stack structures, and a plurality of second stack structures. The substrate includes an array region and a periphery region. The first stack structures are disposed on the substrate in the array region. Each first stack structure sequentially includes: a first tunneling dielectric layer, a first floating gate, a first inter-gate dielectric layer, a first control gate, a first metal layer, a first cap layer, and the first stop layer. The second stack structures are disposed on the substrate in the periphery region. Each second stack structure sequentially includes: a second tunneling dielectric layer, a second floating gate, a second inter-gate dielectric layer, a second control gate, a second metal layer, a second cap layer, and the second stop layer. The first stack structures have a pattern density greater than a pattern density of the second stack structures.

公开(公告)号：US11316106B2

公开(公告)日：2022-04-26

申请号：US17109147

申请日：2020-12-02

Applicant: Winbond Electronics Corp.

Inventor： Chung-Hsuan Wang ,  Yu-Ting Chen ,  Tz-Hau Guo ,  Chang-Hsuan Wu ,  Chiung-Lin Hsu

IPC: H01L45/00 ,  H01L27/24

Abstract: Provided are a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes first, second, and third electrodes, a variable resistance layer, a selection layer, and first and second bit lines. The second electrode and the third electrode are on the first electrode. The second and third electrodes are separated from each other and overlapped with the sidewall and the top surface of the first electrode. The variable resistance layer is between the first and second electrodes and between the first and third electrodes. The selection layer is between the variable resistance layer and the first electrode. The first bit line is on the second electrode and electrically connected to the second electrode via a first contact. The second bit line is on the third electrode and electrically connected to the third electrode via a second contact.