公开(公告)号：US20240234542A9

公开(公告)日：2024-07-11

申请号：US18481433

申请日：2023-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungheon Lee ,  Donghyun Roh ,  Jangho Lee

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A method of manufacturing a semiconductor device, includes forming a mask layer on a semiconductor structure having a plurality of gate lines and a plurality of intergate insulating portions, forming an opening that exposes a cut region of the plurality of gate lines in the mask layer, forming a separation hole by removing a portion of a gate capping layer exposed by the opening, forming a pyrolysis material pattern in the separation hole, forming an etch stop layer on an upper surface of the mask layer and on a side wall portion of the separation hole from which the pyrolysis material pattern is removed, while the pyrolysis material pattern is decomposed and removed, and removing a portion of the gate electrode exposed by the separation hole using the etch stop layer.

公开(公告)号：US20240234527A1

公开(公告)日：2024-07-11

申请号：US18612228

申请日：2024-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Chih Hsiung ,  Jyun-De Wu ,  Yi-Chen Wang ,  Yi-Chun Chang ,  Yuan-Tien Tu

IPC: H01L29/417 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53266 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/66795 ,  H01L29/7851

Abstract: Embodiments provide a dielectric inter block disposed in a metallic region of a conductive line or source/drain contact. A first and second conductive structure over the metallic region may extend into the metallic region on either side of the inter block.
The inter block can prevent etchant or cleaning solution from contacting an interface between the first conductive structure and the metallic region.

公开(公告)号：US20240234413A9

公开(公告)日：2024-07-11

申请号：US18452834

申请日：2023-08-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Natsumi IKEDA ,  Tohru KAWAI

IPC: H01L27/06 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0629 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823462 ,  H01L21/823475 ,  H01L28/20 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/66492 ,  H01L29/7833

Abstract: A semiconductor device including an oscillation circuit includes a MISFET having a halo region formed on a semiconductor substrate and a plurality of MISFETs having no halo regions formed on the semiconductor substrate. Gate electrodes of the plurality of MISFETs having no halo regions are electrically connected to each other. The plurality of MISFETs having no halo regions is used in a pair transistor included in the oscillation circuit.

公开(公告)号：US12033894B2

公开(公告)日：2024-07-09

申请号：US18221754

申请日：2023-07-13

Applicant: Intel Corporation

Inventor： Oleg Golonzka ,  Swaminathan Sivakumar ,  Charles H. Wallace ,  Tahir Ghani

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/306 ,  H01L21/32 ,  H01L21/8234 ,  H01L23/535 ,  H01L27/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/28008 ,  H01L21/30625 ,  H01L21/76805 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66545 ,  H01L21/32

Abstract: Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.

公开(公告)号：US20240222460A1

公开(公告)日：2024-07-04

申请号：US18150021

申请日：2023-01-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jhon-Jhy LIAW

IPC: H01L29/423 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/06 ,  H01L29/08 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/5226 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/78696

Abstract: A method for forming a semiconductor structure is provided. The method includes forming an active region over a substrate. The active region includes a fin element and a plurality of first semiconductor layers and a plurality of second semiconductor layers which are alternately stacked over the fin element. The plurality of first semiconductor layers includes a lowermost first semiconductor layer, and the lowermost first semiconductor layer is thicker than other first semiconductor layers. The method further includes etching the active region to form a first source/drain recess, forming a dielectric isolation feature in the first source/drain recess, forming a first source/drain feature over the dielectric isolation feature in the first source/drain recess, removing the plurality of first semiconductor layers, and forming a gate stack surrounding the second semiconductor layers.

公开(公告)号：US20240222373A1

公开(公告)日：2024-07-04

申请号：US18231187

申请日：2023-08-07

Applicant: TESSERA LLC

Inventor： Marc A. Bergendahl ,  Andrew M. Greene ,  Rajasekhar Venigalla

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/528 ,  H01L23/532 ,  H01L23/62 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/02181 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/5286 ,  H01L23/5329 ,  H01L23/62 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first active region of fin structures from a second active region of fin structures. A conformal etch stop layer is formed in the gate cut trench. A fill material is formed on the conformal etch stop layer filling at least a portion of the gate cut trench. The fill material has a composition that is etched selectively to the conformal etch stop layer. A power rail is formed in the gate cut trench. The conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.

公开(公告)号：US12027585B2

公开(公告)日：2024-07-02

申请号：US18110315

申请日：2023-02-15

Applicant: Intel Corporation

Inventor： Cory Bomberger ,  Anand Murthy ,  Suresh Vishwanath

IPC: H01L29/08 ,  B82Y10/00 ,  H01L21/02 ,  H01L21/8234 ,  H01L23/00 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/36 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L24/09 ,  H01L24/17 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2224/0401

Abstract: Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium and boron. The first and second source or drain structures have a resistivity less than or equal to 0.3 mOhm·cm.

公开(公告)号：US12021025B2

公开(公告)日：2024-06-25

申请号：US18195000

申请日：2023-04-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/5283 ,  H01L27/0886

Abstract: A semiconductor structure (MG) includes a metal gate structure disposed over a semiconductor substrate, a dielectric layer disposed adjacent to the MG, a source/drain (S/D) feature disposed adjacent to the dielectric layer, and a S/D contact disposed over the S/D feature. The S/D contact includes a first metal layer disposed over the S/D feature and a second metal layer disposed on the first metal layer.

公开(公告)号：US20240203985A1

公开(公告)日：2024-06-20

申请号：US18081795

申请日：2022-12-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Nicholas Anthony Lanzillo ,  Albert M. Chu ,  Brent A. Anderson ,  Lawrence A. Clevenger

IPC: H01L27/088 ,  H01L21/822 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L27/088 ,  H01L21/8221 ,  H01L21/823475 ,  H01L21/823487 ,  H01L29/41733 ,  H01L29/78642

Abstract: Embodiments are disclosed for a semiconductor device including a top layer having a top vertical-transport field effect transistor (VTFET). Further, the semiconductor device includes a bottom layer disposed beneath the top layer, wherein the bottom layer includes a first bottom VTFET. Additionally, the semiconductor device includes a first frontside contact that wires, through a first backside contact and a first local interconnect, a bottom source/drain epitaxial of the first bottom VTFET to the back end of line interconnect.

公开(公告)号：US12015027B2

公开(公告)日：2024-06-18

申请号：US17851047

申请日：2022-06-28

Applicant: Innolux Corporation

Inventor： Tang Chin Hung ,  Chin-Lung Ting ,  Chung-Kuang Wei ,  Ker-Yih Kao ,  Tong-Jung Wang ,  Chih-Yung Hsieh ,  Hao Jung Huang ,  I-Yin Li ,  Chia-Chi Ho ,  Yi Hung Lin ,  Cheng-Hsu Chou ,  Chia-Ping Tseng

IPC: H01L27/06 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/93 ,  H01L23/538

CPC classification number: H01L27/0629 ,  H01L21/823475 ,  H01L23/5223 ,  H01L29/93 ,  H01L23/5385 ,  H01L27/0694

Abstract: The disclosure provides an electromagnetic wave adjustment apparatus includes a control circuit, a transistor circuit die and an electronic assembly. The transistor circuit die receives a control signal from the control circuit and drives the electronic assembly.