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公开(公告)号：US09006795B2
公开(公告)日：2015-04-14
申请号：US14180818
申请日：2014-02-14
Applicant: SanDisk 3D LLC
Inventor： Xiaoyu Yang , Roy E. Scheuerlein , Feng Li , Albert T. Meeks
CPC classification number: H01L45/12 , G11C17/00 , G11C17/16 , H01L23/5252 , H01L27/101 , H01L45/04 , H01L45/146 , H01L2924/0002 , H01L2924/00
Abstract: A memory cell is provided that includes a diode and a resistance-switching material layer coupled in series with the diode. The resistance-switching material layer has a thickness between 20 and 65 angstroms. Other aspects are also provided.
Abstract translation: 提供存储单元，其包括与二极管串联耦合的二极管和电阻切换材料层。 电阻切换材料层的厚度为20至65埃。 还提供其他方面。
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32.发明申请DIELECTRIC-BASED MEMORY CELLS HAVING MULTI-LEVEL ONE-TIME PROGRAMMABLE AND BI-LEVEL REWRITEABLE OPERATING MODES AND METHODS OF FORMING THE SAME 审中-公开具有多级一次可编程和双层可操作操作模式的基于介质的存储器单元及其形成方法公开(公告)号：US20140241031A1
公开(公告)日：2014-08-28
申请号：US13780089
申请日：2013-02-28
Applicant: SANDISK 3D LLC
Inventor： Abhijit Bandyopadhyay , Tanmay Kumar , Scott Brad Herner , Christopher J. Petti , Roy E. Scheuerlein
IPC: H01L27/112 , G11C17/16
CPC classification number: G11C17/165 , G11C11/5692 , G11C17/18 , H01L27/1021 , H01L27/11206 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L29/8615 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/1675
Abstract: In some aspects, a memory cell is provided that includes a steering element and a memory element. The memory element includes a first conductive material layer, a first dielectric material layer disposed above the first conductive material layer, a second conductive material layer disposed above the first dielectric material layer, a second dielectric material layer disposed above the second conductive material layer, and a third conductive material layer disposed above the second dielectric material layer. One or both of the first conductive material layer and the second conductive material layer comprise a stack of a metal material layer and a highly doped semiconductor material layer. Numerous other aspects are provided.
Abstract translation: 在一些方面，提供了包括转向元件和存储元件的存储单元。 存储元件包括第一导电材料层，设置在第一导电材料层上方的第一介电材料层，设置在第一介电材料层上方的第二导电材料层，设置在第二导电材料层上方的第二介电材料层，以及 设置在所述第二介电材料层上方的第三导电材料层。 第一导电材料层和第二导电材料层中的一个或两个包括金属材料层和高掺杂半导体材料层的堆叠。 提供了许多其他方面。
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33.发明申请Set/Reset Algorithm Which Detects And Repairs Weak Cells In Resistive-Switching Memory Device 有权在电阻式切换存储器件中检测和修复弱电池的设置/复位算法公开(公告)号：US20140233299A1
公开(公告)日：2014-08-21
申请号：US13772729
申请日：2013-02-21
Applicant: SANDISK 3D LLC
Inventor： Zhida Lan , Roy E. Scheuerlein , Thomas Yan
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C11/5678 , G11C13/0002 , G11C13/0064 , G11C29/4401 , G11C29/50008 , G11C2013/0073 , G11C2029/5002
Abstract: A resistance-switching memory cell is programmed in a set or reset operation which tests the stability of the cell. A first programming phase using program voltages which increase in magnitude or duration until a program verify test is passed. A stability test phase is then performed to evaluate a stability of the memory cell. The stability test phase determines whether the memory cell is weak and likely to transition out of the set or reset state by applying one or more disturb pulses and performing one or more stability verify tests. The disturb pulses can have a reduced magnitude or duration compared to the program voltages. If the stability test phase indicates the memory cell is not stable, a second programming phase is performed. If the stability test phase indicates the memory cell is stable, the operation is concluded.
Abstract translation: 电阻切换存储单元在设置或复位操作中被编程，该操作测试单元的稳定性。 使用程序电压的第一个编程阶段，在程序验证测试通过之前，幅度或持续时间会增加。 然后执行稳定性测试阶段以评估存储器单元的稳定性。 稳定性测试阶段通过施加一个或多个干扰脉冲并执行一个或多个稳定性验证测试来确定存储器单元是否弱并且可能转移到设置或复位状态之外。 与编程电压相比，干扰脉冲可以具有减小的幅度或持续时间。 如果稳定性测试阶段指示存储单元不稳定，则执行第二编程阶段。 如果稳定性测试阶段表明存储单元稳定，则操作结束。
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34.发明申请公开(公告)号：US20130314971A1
公开(公告)日：2013-11-28
申请号：US13678894
申请日：2012-11-16
Applicant: SanDisk 3D LLC
Inventor： Xiaoyu Yang , Roy E. Scheuerlein , Feng Li , Albert T. Meeks
CPC classification number: H01L45/12 , G11C17/00 , G11C17/16 , H01L23/5252 , H01L27/101 , H01L45/04 , H01L45/146 , H01L2924/0002 , H01L2924/00
Abstract: Methods involve using a memory array having memory cells comprising a diode and an antifuse, in which the antifuse is made smaller and programmed at lower voltage by using an antifuse material having a higher dielectric constant and a higher acceleration factor than those of silicon dioxide, and in which the diode is made of a material having a lower band gap than that of silicon. Such memory arrays can be made to have long operating lifetimes by using the high acceleration factor and lower band gap materials. Antifuse materials having dielectric constants between 5 and 27, for example, hafnium silicon oxynitride or hafnium silicon oxide, are particularly effective. Diode materials with band gaps lower than that of silicon, such as germanium or a silicon-germanium alloy, are particularly effective.
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公开(公告)号：US20130242681A1
公开(公告)日：2013-09-19
申请号：US13890622
申请日：2013-05-09
Applicant: SanDisk 3D LLC
Inventor： Tyler J. Thorp , Roy E. Scheuerlein
IPC: G11C7/12
CPC classification number: G11C7/12 , G11C7/065 , G11C8/08 , G11C13/0004 , G11C13/0023 , G11C13/0061 , G11C13/0069
Abstract: A method is provided for programming a memory cell having a first terminal coupled to a word line and a second terminal coupled to a bit line. During a first predetermined time interval, the word line is switched from a first standby voltage to a first voltage, the bit line is switched from a second standby voltage to a predetermined voltage, and a voltage drop across the first and second terminals is a safe voltage that does not program the memory cell. During a second predetermined time interval, the word line is switched from the first voltage to a second voltage, and a voltage drop across the first and second terminals is a programming voltage that is sufficient to program the memory cell. Numerous other aspects are provided.
Abstract translation: 提供了一种用于对具有耦合到字线的第一端子和耦合到位线的第二端子的存储单元进行编程的方法。 在第一预定时间间隔期间，字线从第一备用电压切换到第一电压，位线从第二待机电压切换到预定电压，并且跨第一和第二端子的电压降是安全的 不对存储单元进行编程的电压。 在第二预定时间间隔期间，字线从第一电压切换到第二电压，并且跨越第一和第二端子的电压降是足以编程存储器单元的编程电压。 提供了许多其他方面。
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Patent Agency Ranking
公开(公告)号：US20130170283A1
公开(公告)日：2013-07-04
申请号：US13709349
申请日：2012-12-10
Applicant: Sandisk 3D LLC
Inventor： Zhida Lan , Roy E. Scheuerlein , Tong Zhang , Kun Hou , Perumal Ratnam
IPC: G11C13/00
CPC classification number: G11C13/0097 , G11C13/0002 , G11C13/0007 , G11C13/003 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0083 , G11C2213/32 , G11C2213/52 , G11C2213/71 , G11C2213/77 , H01L27/2454 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1253 , H01L45/145 , H01L45/146
Abstract: A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are provided across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that the bit line acts as a cathode and the word line acts as an anode, with the cathode having a lower electron injection energy barrier to the switching material than the anode.
Abstract translation: 存储元件的三维阵列，其响应于在其上施加的电压差而可逆地改变电导水平。 存储元件设置在跨越半导体衬底的不同距离上的多个平面中。 所有平面的存储元件所连接的位线从衬底垂直定向并穿过多个平面。 存储器元件可以被设置为低电阻状态，并且在标准操作期间通过偏置字线和位线上的适当电压而复位到高电阻状态。 在标准操作之前，存储元件进行成形操作，在此期间，通过位线的电流受到限制。 在具有极性的成形期间，将形成电压施加到存储元件，使得位线用作阴极，并且字线用作阳极，阴极与开关材料相比具有较低的电子注入能量势垒。
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公开(公告)号：US09646688B2
公开(公告)日：2017-05-09
申请号：US14746003
申请日：2015-06-22
Applicant: SanDisk 3D LLC
Inventor： Roy E. Scheuerlein
CPC classification number: G11C13/0033 , G11C5/025 , G11C8/08 , G11C13/0002 , G11C13/0026 , G11C13/0028 , G11C13/0069 , H01L27/0688 , H01L27/115 , H01L27/2454 , H01L27/2463 , H01L27/2481 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/165 , H01L45/1683
Abstract: A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.
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公开(公告)号：US20160133325A1
公开(公告)日：2016-05-12
申请号：US14996144
申请日：2016-01-14
Applicant: SANDISK 3D LLC
Inventor： Zhida Lan , Roy E. Scheuerlein , Tong Zhang , Kun Hou , Perumal Ratnam
IPC: G11C13/00
CPC classification number: G11C13/0097 , G11C13/0002 , G11C13/0007 , G11C13/003 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0083 , G11C2213/32 , G11C2213/52 , G11C2213/71 , G11C2213/77 , H01L27/2454 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1253 , H01L45/145 , H01L45/146
Abstract: A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that a higher voltage is applied to anodes and a lower voltage to cathodes.
Abstract translation: 存储元件的三维阵列，其响应于在其上施加的电压差而可逆地改变电导水平。 存储器元件可以被设置为低电阻状态，并且在标准操作期间通过偏置字线和位线上的适当电压而复位到高电阻状态。 在标准操作之前，存储元件进行成形操作，在此期间，通过位线的电流受到限制。 在成形期间，将形成电压施加到存储元件，其极性使得较高的电压被施加到阳极，而较低的电压施加到阴极。
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公开(公告)号：US09269425B2
公开(公告)日：2016-02-23
申请号：US13709349
申请日：2012-12-10
Applicant: SANDISK 3D LLC
Inventor： Zhida Lan , Roy E. Scheuerlein , Tong Zhang , Kun Hou , Perumal Ratnam
CPC classification number: G11C13/0097 , G11C13/0002 , G11C13/0007 , G11C13/003 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0083 , G11C2213/32 , G11C2213/52 , G11C2213/71 , G11C2213/77 , H01L27/2454 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1253 , H01L45/145 , H01L45/146
Abstract: A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that a higher voltage is applied to anodes and a lower voltage to cathodes.
Abstract translation: 存储元件的三维阵列，其响应于在其上施加的电压差而可逆地改变电导水平。 存储器元件可以被设置为低电阻状态，并且在标准操作期间通过偏置字线和位线上的适当电压而复位到高电阻状态。 在标准操作之前，存储元件进行成形操作，在此期间，通过位线的电流受到限制。 在成形期间，将形成电压施加到存储元件，其极性使得较高的电压被施加到阳极，而较低的电压施加到阴极。
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公开(公告)号：US09202539B2
公开(公告)日：2015-12-01
申请号：US14290888
申请日：2014-05-29
Applicant: SanDisk 3D LLC
Inventor： Tyler J. Thorp , Roy E. Scheuerlein
CPC classification number: G11C7/12 , G11C7/065 , G11C8/08 , G11C13/0004 , G11C13/0023 , G11C13/0061 , G11C13/0069
Abstract: A method is provided for programming a memory cell having a first terminal coupled to a word line and a second terminal coupled to a bit line. During a first predetermined time interval, the word line is switched from a first standby voltage to a first voltage, the bit line is switched from a second standby voltage to a predetermined voltage, and a voltage drop across the first and second terminals is a safe voltage that does not program the memory cell. During a second predetermined time interval, the word line is switched from the first voltage to a second voltage, and a voltage drop across the first and second terminals is a programming voltage that is sufficient to program the memory cell. Numerous other aspects are provided.
Abstract translation: 提供了一种用于对具有耦合到字线的第一端子和耦合到位线的第二端子的存储单元进行编程的方法。 在第一预定时间间隔期间，字线从第一备用电压切换到第一电压，位线从第二待机电压切换到预定电压，并且跨第一和第二端子的电压降是安全的 不对存储单元进行编程的电压。 在第二预定时间间隔期间，字线从第一电压切换到第二电压，并且跨越第一和第二端子的电压降是足以编程存储器单元的编程电压。 提供了许多其他方面。
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