公开(公告)号：US20170011993A1

公开(公告)日：2017-01-12

申请号：US15205991

申请日：2016-07-08

Applicant: Broadcom Corporation

Inventor： Sam Ziqun ZHAO ,  Sam Komarapalayam Karikalan ,  Edward Law ,  Rezaur Rahman Khan ,  Pieter Vorenkamp

IPC: H01L23/498 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49822 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2224/81

Abstract: Semiconductor devices and manufacturing methods are provided for using a Recon interposer that provides a high density interface between the active semiconductor die and the semiconductor substrate and also provides the pitch fan-out. For example, a circuit assembly includes a silicon pad layer including a plurality of metal pads, each metal pad configured to receive a corresponding bump of a plurality of bumps. The circuit assembly further includes an oxide layer disposed on the silicon pad layer and an interposer dielectric layer disposed on the oxide layer. The interposer dielectric layer includes a plurality of routing traces that connect a top surface of the redistribution layer to a bottom surface of the interposer dielectric layer. The circuit assembly further includes an integrated circuit (IC) die attached to the plurality of routing traces at the top surface of the interposer dielectric layer using a plurality of IC bumps and an encapsulating material encapsulating at least a portion of the silicon pad layer, the oxide layer, the interposer dielectric layer, and the IC die to provide structural support for the circuit assembly.

Abstract translation: 提供半导体器件和制造方法，用于使用在活性半导体管芯和半导体衬底之间提供高密度界面的Recon插入件，并且还提供间距扇出。 例如，电路组件包括包括多个金属焊盘的硅焊盘层，每个金属焊盘被配置为接收多个凸块的相应凸块。 电路组件还包括设置在硅衬垫层上的氧化物层和设置在氧化物层上的介入层电介质层。 中介层介电层包括将再分布层的顶表面连接到插入层介电层的底表面的多个布线迹线。 电路组件还包括使用多个IC凸块和封装硅衬垫层的至少一部分的封装材料，在内插器电介质层的顶表面处附接到多个布线迹线的集成电路（IC）裸片， 氧化层，中介层介电层和IC芯片，为电路组件提供结构支撑。

公开(公告)号：US20160190057A1

公开(公告)日：2016-06-30

申请号：US15061747

申请日：2016-03-04

Applicant: BROADCOM CORPORATION

Inventor： Sam Ziqun Zhao ,  Rezaur Rahman Khan

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/32 ,  H01L25/16

CPC classification number: H01L23/49833 ,  H01L23/3142 ,  H01L23/32 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/18 ,  H01L2223/6677 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/32265 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/83101 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19102 ,  H01L2924/19105 ,  H01L2924/3511 ,  H05K1/186 ,  H05K3/4046 ,  H05K3/4688 ,  H05K2201/0218 ,  H05K2201/09609 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2201/2036 ,  H05K2203/041 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2924/0665 ,  H01L2224/81 ,  H01L2924/00012

Abstract: Various examples are provided for interconnection structures for molded IC packages. In one example, among others, an IC package includes a substrate and an interposer. A plurality of conductive elements provide physical and electrical contact between a surface of the substrate and a surface of the interposer. A standoff element disposed between the surfaces of the substrate and interposer provides a minimum spacing between the surfaces of the substrate and interposer. In some implementations, a standoff element is disposed between an IC die disposed on the surface of the substrate and the surface of the interposer. In another example, a method includes coupling conductive elements to a surface of an interposer, attaching a standoff element, coupling the conductive elements to a surface of a substrate, and forming an embedded layer between the interposer and substrate. The standoff element defines a minimum gap between the interposer and the substrate.

Abstract translation: 为模制IC封装的互连结构提供了各种实例。 在一个示例中，其中，IC封装包括基板和插入件。 多个导电元件在基板的表面和插入件的表面之间提供物理和电接触。 设置在基板和插入件的表面之间的间隔元件在基板和插入件的表面之间提供最小的间隔。 在一些实施方案中，支架元件设置在设置在基板的表面上的IC管芯和插入件的表面之间。 在另一示例中，一种方法包括将导电元件耦合到插入件的表面，附接支座元件，将导电元件连接到基板的表面，以及在插入器和基板之间形成嵌入层。 支座元件限定了插入件和基板之间的最小间隙。

公开(公告)号：US09236442B2

公开(公告)日：2016-01-12

申请号：US13725699

申请日：2012-12-21

Applicant: Broadcom Corporation

Inventor： Milind S. Bhagavat ,  Sampath Komarapalayam Velayudham Karikalan ,  Rezaur Rahman Khan

IPC: H01L29/00 ,  H01L29/66 ,  H01L27/08 ,  H01L29/94 ,  H01L21/48 ,  H01L25/16 ,  H01L21/768 ,  H01L23/14 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L29/66181 ,  H01L21/486 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/16 ,  H01L27/0805 ,  H01L29/945 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13063 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Methods and apparatuses are described for integration of integrated circuit die and silicon-based trench capacitors using silicon-level connections to reduce connection lengths, parasitics and necessary capacitance magnitudes and volumes. A trench capacitor can be fabricated on silicon and mounted on or embedded in a chip or one or more sides of a through silicon interposer (TSI) for silicon-level connections to chip circuitry. Aspect ratio dependent, as opposed to trench diameter or trench depth dependent, trench capacitors formed by a dense array of high aspect ratio trenches with thin, high permittivity dielectric increase capacitance per unit area and volume, resulting in thin, high capacitance trench capacitors having thickness equal to or less than chip thickness.

Abstract translation: 描述了集成电路管芯和使用硅层连接的硅基沟槽电容器的方法和装置，以减少连接长度，寄生效应和必要的电容量值和体积。 沟槽电容器可以在硅上制造并且安装在或嵌入在芯片或芯片插入器（TSI）的一侧或多侧上，用于与芯片电路的硅层连接。 长宽比取决于与沟槽直径或沟槽深度相关的沟槽电容器，其由具有薄的高介电常数介电常数的高纵横比沟槽的密集阵列形成，增加了每单位面积和体积的电容，导致薄的高电容沟槽电容器具有厚度 等于或小于芯片厚度。

公开(公告)号：US09230875B2

公开(公告)日：2016-01-05

申请号：US14260872

申请日：2014-04-24

Applicant: Broadcom Corporation

Inventor： Sam Ziqun Zhao ,  Rezaur Rahman Khan

IPC: H04B1/40 ,  H01L23/34 ,  H01L23/552 ,  H01L23/36 ,  H01L23/48 ,  H01L23/498 ,  H01L23/50 ,  H01L23/31 ,  H04B5/00 ,  H04B7/06

CPC classification number: H01L23/34 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/50 ,  H01L23/552 ,  H01L24/73 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H04B1/40 ,  H04B5/0037 ,  H04B5/0068 ,  H04B7/0617 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Embodiments of provide an integrated circuit (IC) device. The IC device can include a substrate having first and second opposing surfaces, an IC die electrically coupled to the first surface of the substrate, a plurality of contact members coupled to the first surface of the substrate, and an interposer. The interposer can include a plurality of contact elements located on a first surface thereof, each conductive element being coupled to a respective one of the plurality of contact members, and an antenna formed using a conductive layer of the interposer, the antenna being electrically coupled to the IC die through at least one of the plurality of contact elements and at least one of the plurality of contact members.

Abstract translation: 提供集成电路（IC）装置的实施例。 IC器件可以包括具有第一和第二相对表面的衬底，电连接到衬底的第一表面的IC管芯，耦合到衬底的第一表面的多个接触构件和插入器。 插入器可以包括位于其第一表面上的多个接触元件，每个导电元件耦合到所述多个接触构件中的相应一个，以及使用所述插入器的导电层形成的天线，所述天线电耦合到 所述IC通过所述多个接触元件中的至少一个和所述多个接触构件中的至少一个接合。

公开(公告)号：US09129980B2

公开(公告)日：2015-09-08

申请号：US13929240

申请日：2013-06-27

Applicant: Broadcom Corporation

Inventor： Rezaur Rahman Khan ,  Sam Ziqun Zhao

IPC: H01L21/44 ,  H01L21/56 ,  H01L23/552 ,  H01L25/10 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L21/565 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/16 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method of manufacturing an integrated circuit (IC) package is provided. The method includes mounting a fast plurality of contact members on a surface of a package member, and coupling a second plurality of contact members located on a first surface of an interposer substrate to corresponding ones of the first plurality of contact members. The interposer substrate is configured such that a circuit member mounted to a second surface of the interposer substrate is electrically coupled to the first plurality of contact members.

Abstract translation: 提供一种制造集成电路（IC）封装的方法。 该方法包括将快速多个接触构件安装在封装构件的表面上，以及将位于中介层基板的第一表面上的第二多个接触构件与第一多个接触构件中的相应接触构件连接。 插入器基板被配置为使得安装到插入器基板的第二表面的电路构件电耦合到第一多个接触构件。

公开(公告)号：US20150206821A1

公开(公告)日：2015-07-23

申请号：US14674769

申请日：2015-03-31

Applicant: Broadcom Corporation

Inventor： Sam Ziqun ZHAO ,  Arpit Mittal ,  Rezaur Rahman Khan

IPC: H01L23/373 ,  F28F21/02 ,  F28F21/08 ,  H01L21/48

CPC classification number: H01L23/373 ,  B82Y10/00 ,  B82Y99/00 ,  F28F21/02 ,  F28F21/081 ,  H01L21/02112 ,  H01L21/4882 ,  H01L23/3735 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L29/0669 ,  H01L29/0676 ,  H01L51/0048 ,  H01L2223/64 ,  H01L2224/16225 ,  H01L2224/2908 ,  H01L2224/29193 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83192 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/167 ,  H01L2924/351 ,  H05K1/0203 ,  Y10S977/742 ,  H01L2924/00

Abstract: In an embodiment, a thermal interface material (TIM) is provided. The TIM includes first and a second layers of a first transition metal, and a third layer including a plurality of carbon nanotubes supported in a flexible polymer matrix and a second transition metal coupled to sidewalls of carbon nanotubes. The first and second metal layers are in contact with first and second ends of carbon nanotube. The TIM further includes fourth and fifth layers of an alloy material coupled to the first and second metal layers, respectively. The carbon nanotube based TIM including the layers with transition metal allow improved heat transfer from an integrated circuit die to a heat spreader.

Abstract translation: 在一个实施例中，提供了热界面材料（TIM）。 TIM包括第一和第二层第一过渡金属，第三层包括支撑在柔性聚合物基体中的多个碳纳米管和耦合到碳纳米管的侧壁的第二过渡金属。 第一和第二金属层与碳纳米管的第一和第二端接触。 TIM还包括分别耦合到第一和第二金属层的合金材料的第四层和第五层。 包括具有过渡金属的层的基于碳纳米管的TIM允许改进从集成电路管芯到散热器的热传递。

公开(公告)号：US20140291818A1

公开(公告)日：2014-10-02

申请号：US13850827

申请日：2013-03-26

Applicant: BROADCOM CORPORATION

Inventor： Sam Ziqun ZHAO ,  Rezaur Rahman Khan

IPC: H01L23/552 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/1815 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In embodiments described herein, an integrated circuit (IC) package is provided. The IC package can include a substrate having opposing first and second surfaces, an IC die coupled to the first surface of the substrate, a first plurality of conductive elements coupled to conductive regions on the first surface of the substrate, an interposer having opposing first and second surfaces, and a second plurality of conductive elements coupled to conductive regions on the first surface of the interposer. The second surface of the substrate is configured be coupled to at least one device. Each of the first plurality of conductive elements is electrically coupled to a respective one of the second plurality of conductive elements. The interposer is configured to be attached to a printed circuit board (PCB).

Abstract translation: 在这里描述的实施例中，提供了集成电路（IC）封装。 IC封装可以包括具有相对的第一和第二表面的衬底，耦合到衬底的第一表面的IC管芯，耦合到衬底的第一表面上的导电区域的第一多个导电元件，具有相对的第一和第二表面的插入件 第二表面和耦合到插入件的第一表面上的导电区域的第二多个导电元件。 衬底的第二表面被配置为耦合到至少一个器件。 第一多个导电元件中的每一个电耦合到第二多个导电元件中的相应一个。 插入器被配置为附接到印刷电路板（PCB）。

公开(公告)号：US08829656B2

公开(公告)日：2014-09-09

申请号：US14079571

申请日：2013-11-13

Applicant: Broadcom Corporation

Inventor： Sam Ziqun Zhao ,  Rezaur Rahman Khan

IPC: H01L29/40 ,  H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L23/495 ,  H01L25/10 ,  H01L23/498 ,  H01L23/538 ,  H01L23/14 ,  H01L25/00

CPC classification number: H01L23/481 ,  H01L21/4857 ,  H01L23/14 ,  H01L23/145 ,  H01L23/147 ,  H01L23/49506 ,  H01L23/49575 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/97 ,  H01L25/00 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/14183 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/30183 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1515 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present application discloses various implementations of a semiconductor package including an organic substrate and one or more interposers having through-semiconductor vias (TSVs). Such a semiconductor package may include a contiguous organic substrate having a lower substrate segment including first and second pluralities of lower interconnect pads, the second plurality of lower interconnect pads being disposed in an opening of the lower substrate segment. The contiguous organic substrate may also include an upper substrate segment having an upper width and including first and second pluralities of upper interconnect pads. In addition, the semiconductor package may include at least one interposer having TSVs for electrically connecting the first and second pluralities of lower interconnect pads to the first and second pluralities of upper interconnect pads. The interposer has an interposer width less than the upper width of the upper substrate segment.

Abstract translation: 本申请公开了包括有机衬底和具有贯通半导体通孔（TSV）的一个或多个中介层的半导体封装的各种实施方式。 这种半导体封装可以包括具有包括第一和第二多个下部互连焊盘的下部衬底区段的连续有机衬底，第二多个下部互连焊盘设置在下部衬底段的开口中。 连续的有机衬底还可以包括具有上部宽度并包括第一和第二多个上部互连焊盘的上部衬底区段。 此外，半导体封装可以包括具有TSV的至少一个插入器，用于将第一和第二多个下部互连焊盘电连接到第一和第二多个上部互连焊盘。 插入器具有小于上基板段的上宽度的插入器宽度。

公开(公告)号：US20140103505A1

公开(公告)日：2014-04-17

申请号：US13653330

申请日：2012-10-16

Applicant: BROADCOM CORPORATION

Inventor： Sam Ziqun Zhao ,  Rezaur Rahman Khan

IPC: H01L23/495 ,  H01L23/34 ,  H01L21/78

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/4334 ,  H01L23/49551 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Methods, systems, and apparatuses for integrated circuit packages are provided. An integrated circuit package, such as a quad flat no-lead (QFN) package, includes a plurality of peripherally positioned leads, a heat spreader, an integrated circuit die, and an encapsulating material. The peripherally positioned leads are attached to a first surface of the heat spreader, and the die is attached to the first surface of the heat spreader within a ring formed by the leads. The encapsulating material encapsulates the die on the heat spreader, encapsulates bond wires, and fills a space between the leads. A second surface of the heat spreader is exposed from the package. End portions of the leads have surfaces that are flush with a surface of the package opposite the second surface of the heat spreader, and that are used as lands for the package.

Abstract translation: 提供了集成电路封装的方法，系统和装置。 诸如四方扁平无引线（QFN）封装的集成电路封装包括多个外围定位的引线，散热器，集成电路管芯和封装材料。 外围定位的引线附接到散热器的第一表面，并且模具附接到由引线形成的环内的散热器的第一表面。 封装材料将模具封装在散热器上，封装接合线，并填充引线之间的空间。 散热器的第二表面从包装中暴露出来。 引线的端部具有与封套的与散热器的第二表面相对的表面齐平的表面，并且用作封装的焊盘。

公开(公告)号：US20140061886A1

公开(公告)日：2014-03-06

申请号：US14078799

申请日：2013-11-13

Applicant: Broadcom Corporation

Inventor： Sam Ziqun Zhao ,  Rezaur Rahman Khan

IPC: H01L23/495

CPC classification number: H01L23/481 ,  H01L21/4857 ,  H01L23/14 ,  H01L23/145 ,  H01L23/147 ,  H01L23/49506 ,  H01L23/49575 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/97 ,  H01L25/00 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/14183 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/30183 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1515 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present application discloses various implementations of a semiconductor package including an organic substrate and one or more interposers having through-semiconductor vias (TSVs). Such a semiconductor package may include a contiguous organic substrate having a lower substrate segment including first and second pluralities of lower interconnect pads, the second plurality of lower interconnect pads being disposed in an opening of the lower substrate segment. The contiguous organic substrate may also include an upper substrate segment having an upper width and including first and second pluralities of upper interconnect pads. In addition, the semiconductor package may include at least one interposer having TSVs for electrically connecting the first and second pluralities of lower interconnect pads to the first and second pluralities of upper interconnect pads. The interposer has an interposer width less than the upper width of the upper substrate segment.

Abstract translation: 本申请公开了包括有机衬底和具有贯通半导体通孔（TSV）的一个或多个中介层的半导体封装的各种实施方式。 这种半导体封装可以包括具有包括第一和第二多个下部互连焊盘的下部衬底区段的连续有机衬底，第二多个下部互连焊盘设置在下部衬底段的开口中。 连续的有机衬底还可以包括具有上部宽度并包括第一和第二多个上部互连焊盘的上部衬底区段。 此外，半导体封装可以包括具有TSV的至少一个插入器，用于将第一和第二多个下部互连焊盘电连接到第一和第二多个上部互连焊盘。 插入器具有小于上基板段的上宽度的插入器宽度。