公开(公告)号：US07884349B2

公开(公告)日：2011-02-08

申请号：US12283339

申请日：2008-09-11

Applicant: Darrell Rinerson ,  Steve Kuo-Ren Hsia ,  Steven W. Longcor ,  Wayne Kinney ,  Edmond Ward ,  Christophe J. Chevallier

Inventor： Darrell Rinerson ,  Steve Kuo-Ren Hsia ,  Steven W. Longcor ,  Wayne Kinney ,  Edmond Ward ,  Christophe J. Chevallier

IPC: H01L29/06

CPC classification number: H01L27/101 ,  G11C11/00 ,  G11C11/56 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/24 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/00 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/147

Abstract: A memory cell including a memory element and a non-ohmic device (NOD) that are electrically in series with each other is disclosed. The NOD comprises a semiconductor based selection device operative to electrically isolate the memory element from a range of voltages applied across the memory cell that are not read voltages operative read stored data from the memory element or write voltages operative to write data to the memory element. The selection device may comprise a pair of diodes that are electrically in series with each other and disposed in a back-to-back configuration. The memory cell may be fabricated over a substrate (e.g., a silicon wafer) that includes active circuitry. The selection device and the semiconductor materials (e.g., poly-silicon) that form the selection device are fabricated above the substrate and are integrated with other thin film layers of material that form the memory cell.

Abstract translation: 公开了一种包括彼此电串联的存储元件和非欧姆器件（NOD）的存储单元。 NOD包括基于半导体的选择装置，其操作以将存储器元件与施加在存储器单元上的电压范围电隔离，所述电压范围不是读取电压，从存储元件读取存储的数据，或者写入电压可操作以将数据写入存储器元件。 选择装置可以包括彼此电连接并以背对背配置设置的一对二极管。 可以在包括有源电路的衬底（例如，硅晶片）上制造存储器单元。 形成选择装置的选择装置和半导体材料（例如，多晶硅）制造在衬底之上，并与形成存储单元的材料的其它薄膜层集成。

公开(公告)号：US20070152202A1

公开(公告)日：2007-07-05

申请号：US11324622

申请日：2006-01-03

Applicant: Wayne Kinney

Inventor： Wayne Kinney

IPC: B66F5/00

CPC classification number: B66F7/26 ,  B66F3/245 ,  B66F5/04

Abstract: A roller jack assembly is provided for supporting at least one roller of a dozer. The roller jack assembly includes a frame assembly, a jack frame assembly, and a jack assembly. The frame assembly is disposable on a supporting structure. The jack frame assembly is supported by the frame assembly. The jack frame assembly has a jack frame and means for selectively moving the jack frame along the frame assembly. The jack assembly is supported by the jack frame of the jack frame assembly. The jack assembly has a base frame, a jack supported by the base frame, means for selectively moving the base frame along the jack frame and a roller support member supported by the jack for engaging and supporting at least one roller of the dozer.

Abstract translation: 提供了用于支撑推土机的至少一个辊的滚子千斤顶组件。 滚子千斤顶组件包括框架组件，千斤顶框架组件和千斤顶组件。 框架组件一次性在支撑结构上。 插座框架组件由框架组件支撑。 插座框架组件具有插座框架和用于沿着框架组件选择性地移动插座框架的装置。 千斤顶组件由千斤顶框架组件的千斤顶框架支撑。 千斤顶组件具有底架，由底架支撑的千斤顶，用于选择性地沿底座框架移动底座的装置和由千斤顶支撑的滚子支撑构件，用于接合和支撑推土机的至少一个滚子。

公开(公告)号：US07095643B2

公开(公告)日：2006-08-22

申请号：US11151880

申请日：2005-06-13

Applicant: Darrell Rinerson ,  Christophe Chevallier ,  Wayne Kinney ,  Steven W. Longcor ,  Edmond R. Ward

Inventor： Darrell Rinerson ,  Christophe Chevallier ,  Wayne Kinney ,  Steven W. Longcor ,  Edmond R. Ward

IPC: G11C5/06

CPC classification number: G11C13/0007 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C2213/31

Abstract: A re-writable memory with multiple memory layers. Using both terminals of a memory cell in a stacked cross point structure for selection purposes allows multiple layers of conductive lines to be selected as long as there is only one memory cell that has two terminals selected. Sharing logic over multiple layers allows driver sets to be reused.

Abstract translation: 具有多个内存层的可重写内存。 只要存在只有一个选择了两个端子的存储单元，就可以选择使用层叠交叉点结构中的存储单元的两个端子进行选择，以便选择多层导电线。 通过多层共享逻辑可以重新使用驱动程序集。

公开(公告)号：US07079442B2

公开(公告)日：2006-07-18

申请号：US10612733

申请日：2003-07-01

Applicant: Darrell Rinerson ,  Christophe J. Chevallier ,  Steven W. Longcor ,  Wayne Kinney ,  Edmond R. Ward

Inventor： Darrell Rinerson ,  Christophe J. Chevallier ,  Steven W. Longcor ,  Wayne Kinney ,  Edmond R. Ward

IPC: G11C7/00

CPC classification number: G11C5/025 ,  G11C11/16 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/31

Abstract: Layouts of driver sets in a cross point memory array. Since both terminals of a memory cell in a cross point structure are typically used for selection purposes, dedicated driver sets are typically required for both x and y directions. By fabricating the cross point array above the driver circuitry, several different driver set layouts can be utilized that allow for varying designs.

Abstract translation: 在交叉点存储器阵列中布置驱动程序集。 由于交叉点结构中的存储单元的两个端子通常用于选择目的，所以通常对于x和y方向都需要专用的驱动器组。 通过在驱动器电路上方制造交叉点阵列，可以利用允许不同设计的几种不同的驱动器组布局。

公开(公告)号：US07071008B2

公开(公告)日：2006-07-04

申请号：US10604606

申请日：2003-08-04

Applicant: Darrell Rinerson ,  Wayne Kinney ,  Christophe J. Chevallier ,  Steven W. Longcor ,  Edmond R. Ward ,  Steve Kuo-Ren Hsia

Inventor： Darrell Rinerson ,  Wayne Kinney ,  Christophe J. Chevallier ,  Steven W. Longcor ,  Edmond R. Ward ,  Steve Kuo-Ren Hsia

IPC: H01L21/00 ,  H01L21/20

CPC classification number: G11C13/003 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/2418 ,  H01L27/2436 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/147 ,  H01L45/165

Abstract: A multi-resistive state material that uses dopants is provided. A multi-resistive state material can be used in a memory cell to store information. However, a multi-resistive state material may not have electrical properties that are appropriate for a memory device. Intentionally doping a multi-resistive state material to modify the electrical properties can, therefore, be desirable.

Abstract translation: 提供了使用掺杂剂的多阻态材料。 可以在存储器单元中使用多电阻状态材料来存储信息。 然而，多阻态材料可能不具有适合于存储器件的电气特性。 因此，有意地掺杂多电阻状态材料以改变电性能是可取的。

公开(公告)号：US06970375B2

公开(公告)日：2005-11-29

申请号：US10330170

申请日：2002-12-26

Applicant: Darrell Rinerson ,  Christophe J. Chevallier ,  Steven W. Longcor ,  Edmond R. Ward ,  Wayne Kinney ,  Steve Kuo-Ren Hsia

Inventor： Darrell Rinerson ,  Christophe J. Chevallier ,  Steven W. Longcor ,  Edmond R. Ward ,  Wayne Kinney ,  Steve Kuo-Ren Hsia

IPC: G11C13/00 ,  G11C16/02 ,  H01L27/24 ,  G11C11/00

CPC classification number: G11C13/0007 ,  G11C5/147 ,  G11C11/15 ,  G11C13/0004 ,  G11C2213/31

Abstract: Providing a reference voltage to a cross point memory array. The invention is a cross point memory array and some peripheral circuitry that, when activated, provides a reference voltage to a cross point array in order to prevent unselected conductive array lines from floating to an undesired voltage. The peripheral circuitry can be activated before, after or during selection of a specific memory plug. If the peripheral circuitry is activated during selection, only the unselected conductive array lines should be brought to the reference voltage. Otherwise, all the conductive array lines can be brought to the reference voltage.

Abstract translation: 向交叉点存储器阵列提供参考电压。 本发明是一种交叉点存储器阵列和一些外围电路，当被激活时，它向交叉点阵列提供参考电压，以便防止未选择的导电阵列线漂浮到不需要的电压。 外围电路可在特定内存插头选择之前，之后或期间激​​活。 如果外围电路在选择期间被激活，则只有未选择的导电阵列线才能被带到参考电压。 否则，所有导电阵列线可以被带到参考电压。

公开(公告)号：US20050243595A1

公开(公告)日：2005-11-03

申请号：US10868578

申请日：2004-06-15

Applicant: Darrell Rinerson ,  Christophe Chevallier ,  Philip Swab ,  Steve Hsia ,  John Sanchez ,  Mary Calarrudo ,  Steven Longcor ,  Wayne Kinney

Inventor： Darrell Rinerson ,  Christophe Chevallier ,  Philip Swab ,  Steve Hsia ,  John Sanchez ,  Mary Calarrudo ,  Steven Longcor ,  Wayne Kinney

IPC: G11C11/00 ,  G11C11/56 ,  G11C13/02

CPC classification number: G11C13/0011 ,  G11C11/5614 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/79

Abstract: A memory including a memory element having islands is provided. The memory has address decoding circuitry and an array of memory plugs. The memory plugs include memory element that have island structures of a first material within the bulk of a second material. The island structures are typically nanoparticles. The memory plugs can be placed in a first resistive state at a first write voltage, placed in a second resistive state at a second write voltage, and have its resistive state determined at a read voltage.

Abstract translation: 提供了包括具有岛的存储元件的存储器。 存储器具有地址解码电路和一组存储器插头。 存储器插头包括在第二材料的主体内具有第一材料的岛结构的存储元件。 岛结构通常是纳米颗粒。 存储器插头可以以第一写入电压处于第一电阻状态，以第二写入电压置于第二电阻状态，并且在读取电压下确定其电阻状态。

公开(公告)号：US20050174835A1

公开(公告)日：2005-08-11

申请号：US10773549

申请日：2004-02-06

Applicant: Darrell Rinerson ,  Wayne Kinney ,  Edmond Ward ,  Steve Hsia ,  Steven Longcor ,  Christophe Chevallier ,  John Sanchez ,  Philip Swab

Inventor： Darrell Rinerson ,  Wayne Kinney ,  Edmond Ward ,  Steve Hsia ,  Steven Longcor ,  Christophe Chevallier ,  John Sanchez ,  Philip Swab

IPC: G11C11/16 ,  G11C11/56 ,  G11C13/00 ,  H01L27/24 ,  G11C11/14

CPC classification number: H01L27/2463 ,  G11C11/16 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/24 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633 ,  H01L45/1658

Abstract: A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.

Abstract translation: 提供经处理的导电元件。 可以通过在导电元件上沉积反应性金属或非常薄的材料层来处理导电元件。 反应性金属（或非常薄的材料层）通常将夹在导电元件和电极之间。 该结构还具有非线性IV特性，这在某些阵列中是有利的。

公开(公告)号：US5955758A

公开(公告)日：1999-09-21

申请号：US738789

申请日：1996-10-29

Applicant: Gurtej S. Sandhu ,  Paul Schuele ,  Wayne Kinney

Inventor： Gurtej S. Sandhu ,  Paul Schuele ,  Wayne Kinney

IPC: H01L21/02 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/108

CPC classification number: H01L27/11502 ,  H01L27/1085 ,  H01L27/11507 ,  H01L28/40 ,  H01L27/10852

Abstract: A method of forming a capacitor includes, a) providing a node to which electrical connection to a capacitor is to be made; b) providing an electrically conductive first layer over the node; c) providing an electrically insulative barrier second layer over the first conductive layer; d) providing a third layer over the electrically insulative barrier layer, the third layer comprising a material which is either electrically conductive and resistant to oxidation, or forms an electrically conductive material upon oxidation; e) providing an insulating inorganic metal oxide dielectric layer over the electrically conductive third layer; f) providing an electrically conductive fourth layer over the insulating inorganic metal oxide dielectric layer; and g) providing an electrically conductive interconnect to extend over the second insulative layer and electrically interconnect the first and third conductive layers. A capacitor construction having such a dielectric layer in combination with the barrier layer and electrical interconnect of a first capacitor plate is disclosed.

Abstract translation: 形成电容器的方法包括：a）提供与电容器进行电连接的节点; b）在节点上提供导电的第一层; c）在所述第一导电层之上提供电绝缘阻挡层第二层; d）在电绝缘阻挡层上提供第三层，第三层包括导电并耐氧化的材料，或者在氧化时形成导电材料; e）在导电的第三层之上提供绝缘的无机金属氧化物介电层; f）在绝缘无机金属氧化物介电层上提供导电第四层; 以及g）提供导电互连以在所述第二绝缘层上延伸并且使所述第一和第三导电层电互连。 公开了一种电容器结构，其具有与阻挡层和第一电容器板的电互连结合的这种介电层。

公开(公告)号：US08675389B2

公开(公告)日：2014-03-18

申请号：US13272985

申请日：2011-10-13

Applicant: Christophe Chevallier ,  Steve Kuo-Ren Hsia ,  Wayne Kinney ,  Steven Longcor ,  Darrell Rinerson ,  John Sanchez, Jr. ,  Philip Swab ,  Edmond Ward

Inventor： Christophe Chevallier ,  Steve Kuo-Ren Hsia ,  Wayne Kinney ,  Steven Longcor ,  Darrell Rinerson ,  John Sanchez, Jr. ,  Philip Swab ,  Edmond Ward

IPC: G11C11/21

CPC classification number: H01L27/2463 ,  G11C11/16 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/24 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633 ,  H01L45/1658

Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3—LSCoO or LaNiO3—LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.

Abstract translation: 公开了一种包括导电氧化物电极的存储单元。 存储单元包括用于将数据存储为多个电阻状态的存储元件。 存储元件包括与可包括一层或多层材料的电极接触的导电金属氧化物（CMO）（例如，钙钛矿）层。 这些材料层中的至少一层可以是与CMO接触的导电氧化物（例如，诸如LaSrCoO3-LSCoO或LaNiO3-LNO的钙钛矿）。 可以选择导电氧化物层作为晶种层，以为CMO提供良好的晶格匹配和/或较低的结晶温度。 导电氧化物层也可以与金属层（例如Pt）接触。 存储单元还具有非线性IV特性，这在某些阵列中是有利的，例如非易失性两端交叉点存储阵列。