公开(公告)号：US07804118B2

公开(公告)日：2010-09-28

申请号：US12635181

申请日：2009-12-10

Applicant: Satoru Akiyama ,  Takao Watanabe ,  Yuichi Matsui ,  Masahiko Hiratani

Inventor： Satoru Akiyama ,  Takao Watanabe ,  Yuichi Matsui ,  Masahiko Hiratani

IPC: H01L29/78

CPC classification number: H01L27/10852 ,  H01L23/5223 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory cell capacitor (C3) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M3) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs.

公开(公告)号：US20100237404A1

公开(公告)日：2010-09-23

申请号：US12718002

申请日：2010-03-05

Applicant: KOICHI TOBA ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Satoru Machida ,  Munekatsu Nakagawa ,  Kentaro Saito ,  Toshikazu Matsui ,  Takashi Hashimoto ,  Kosuke Okuyama

Inventor： KOICHI TOBA ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Satoru Machida ,  Munekatsu Nakagawa ,  Kentaro Saito ,  Toshikazu Matsui ,  Takashi Hashimoto ,  Kosuke Okuyama

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/42324 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7885

Abstract: A semiconductor device having a non-volatile memory is disclosed, whose disturb defect can be diminished or prevented. A memory cell of the non-volatile memory has a memory gate electrode formed over a main surface of a semiconductor substrate through an insulating film for charge storage. A first side wall is formed on a side face of the memory gate electrode, and at a side face of the first side wall, a second side wall is formed. On an upper surface of an n+-type semiconductor region for source in the memory cell there is formed a silicide layer whose end portion on the memory gate electrode MG side is defined by the second side wall.

Abstract translation: 公开了一种具有非易失性存储器的半导体器件，其干扰缺陷可被减弱或防止。 非易失性存储器的存储单元具有通过用于电荷存储的绝缘膜形成在半导体衬底的主表面上的存储栅电极。 第一侧壁形成在存储栅电极的侧面上，在第一侧壁的侧面形成有第二侧壁。 在存储单元中用于源极的n +型半导体区域的上表面上形成硅化物层，其存储栅极电极MG侧的端部由第二侧壁限定。

公开(公告)号：US20100231768A1

公开(公告)日：2010-09-16

申请号：US12722121

申请日：2010-03-11

Applicant: Hiroto Utsunomiya ,  Katsumi Dosaka ,  Hiroshi Kato ,  Fukashi Morishita ,  Fumiyasu Sasaki

Inventor： Hiroto Utsunomiya ,  Katsumi Dosaka ,  Hiroshi Kato ,  Fukashi Morishita ,  Fumiyasu Sasaki

IPC: H04N5/335

CPC classification number: H04N5/37455 ,  H03M1/1205 ,  H03M1/144 ,  H03M1/403 ,  H03M1/66 ,  H03M2201/16 ,  H04N5/374 ,  H04N5/3742 ,  H04N5/3765 ,  H04N5/378

Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.

Abstract translation: 提供了包括可以在有限空间中布置的ADC的固态图像拾取装置。 通过垂直读出线输出的像素信号的电位被保持在节点处。 多个电容器电容耦合到保持像素信号的节点。 通过晶体管的控制，通过依次切换电容器对置电极的电压，逐步降低节点的电位。 比较器将节点的电位与像素的暗状态的电位进行比较，并且当节点的电位变得低于黑暗状态的电位时，确定数字值的高位。 此后，开始数字值的低位的转换。 因此，可以简化每个ADC的配置，并将每个ADC排列在有限的空间内。

公开(公告)号：US20100230761A1

公开(公告)日：2010-09-16

申请号：US12720174

申请日：2010-03-09

Applicant: Tadashi Yamaguchi ,  Toshiaki Tsutsumi ,  Satoshi Ogino ,  Kazumasa Yonekura ,  Kenji Kawai ,  Yoshihiro Miyagawa ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Kotaro Kihara

Inventor： Tadashi Yamaguchi ,  Toshiaki Tsutsumi ,  Satoshi Ogino ,  Kazumasa Yonekura ,  Kenji Kawai ,  Yoshihiro Miyagawa ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Kotaro Kihara

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823835 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7843

Abstract: To improve the performance of semiconductor devices. Over an n+-type semiconductor region for source/drain of an n-channel type MISFET and a first gate electrode, and over a p+-type semiconductor region for source/drain of a p-channel type MISFET and a second gate electrode, which are formed over a semiconductor substrate, a metal silicide layer including nickel platinum silicide is formed by a salicide process. After that, a tensile stress film is formed over the whole face of the semiconductor substrate, and then the tensile stress film over the p-channel type MISFET is removed by dry-etching, and, after a compression stress film is formed over the whole face of the semiconductor substrate, the compression stress film over the n-channel type MISFET is removed by dry-etching. The Pt concentration in the metal silicide layer is highest at the surface, and becomes lower as the depth from the surface increases.

Abstract translation: 提高半导体器件的性能。 在用于n沟道型MISFET和第一栅电极的源极/漏极的n +型半导体区域上，以及用于p沟道型MISFET和第二栅电极的源极/漏极的p +型半导体区域上，其中 形成在半导体衬底上，通过自对准硅化物工艺形成包括镍铂硅化物的金属硅化物层。 之后，在半导体基板的整个面上形成拉伸应力膜，然后通过干法蚀刻去除p沟道型MISFET上的拉伸应力膜，并且在整个压电应力膜形成之后 在半导体衬底的表面上，通过干蚀刻去除n沟道型MISFET上的压缩应力膜。 金属硅化物层中的Pt浓度在表面处最高，并且随着从表面的深度增加而变低。

公开(公告)号：US07796426B2

公开(公告)日：2010-09-14

申请号：US12090375

申请日：2005-10-17

Applicant: Osamu Tonomura ,  Norikatsu Takaura ,  Kenzo Kurotsuchi ,  Nozomu Matsuzaki

Inventor： Osamu Tonomura ,  Norikatsu Takaura ,  Kenzo Kurotsuchi ,  Nozomu Matsuzaki

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C7/04 ,  G11C13/0004 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/79

Abstract: A technique capable of improving speed of a set operation, which controls writing rate in a semiconductor device including a memory cell using a phase-change material. The technique uses means for setting a set-pulse voltage to be applied to the phase-change material to have two steps: the first-step voltage sets a temperature of the phase-change memory to a temperature at which the fastest nucleation is obtained; and the second pulse sets the temperature to a temperature at which the fastest crystal growth is obtained, thereby obtaining solid-phase growth of the phase-change material without melting. Moreover, the technique uses means for controlling the two-step voltage applied to the phase-change memory by a two-step voltage applied to a word line capable of reducing the drain current variation.

Abstract translation: 一种能够提高设定操作速度的技术，其控制包括使用相变材料的存储单元的半导体器件的写入速度。 该技术使用用于设定要施加到相变材料的设定脉冲电压的装置以具有两个步骤：第一步骤电压将相变存储器的温度设置为获得最快成核的温度; 并且第二脉冲将温度设定为获得最快的晶体生长的温度，从而获得相变材料的固相生长而不熔化。 此外，该技术使用用于通过施加到能够减小漏极电流变化的字线的两级电压来控制施加到相变存储器的两级电压的装置。

公开(公告)号：US20100229161A1

公开(公告)日：2010-09-09

申请号：US12694657

申请日：2010-01-27

Applicant: Noriyasu MORI

Inventor： Noriyasu MORI

IPC: G06F9/45

CPC classification number: G06F8/456

Abstract: A compile technique is provided for multicore allocation, by which a desired running performance can be achieved. The steps of analyzing a taskization directive, taskizing a specified part, and assigning a specified CPU the task are adopted for the compile technique. According to the program-to-tasks-decomposition compile technique, the multicore decomposition is performed by allocating tasks to CPUs individually while following a task decomposition directive of a main part designated by a user. When no direction is issued concerning a CPU to be allocated, the relation with a principal task is judged from the relation of invocation and the dependency, and CPU to be allocated, and then the CPU to be allocated is determined. In allocation to the CPU, an efficient multicore-task decomposition is achieved in consideration of copy and assignment of one processing to more than one CPU while figuring in the balance between processing speed and resources.

Abstract translation: 提供了一种用于多核分配的编译技术，通过该编译技术可以实现期望的运行性能。 为编译技术采用分析任务指令，指定部分任务以及分配指定CPU任务的步骤。 根据程序到任务分解编译技术，通过在根据用户指定的主要部分的任务分解指令之后单独分配任务来执行多核分解。 当没有关于要分配的CPU的方向发布时，根据调用和依赖关系以及要分配的CPU来判断与主任务的关系，然后确定要分配的CPU。 在分配给CPU时，考虑到将一个处理复制和分配给多个CPU，同时计算处理速度和资源之间的平衡，实现了高效的多核任务分解。

公开(公告)号：US20100227446A1

公开(公告)日：2010-09-09

申请号：US12784876

申请日：2010-05-21

Applicant: Satoshi SAKAI ,  Atsushi Hiraiwa ,  Satoshi Yamamoto

Inventor： Satoshi SAKAI ,  Atsushi Hiraiwa ,  Satoshi Yamamoto

IPC: H01L21/8234

CPC classification number: H01L21/823462 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878

Abstract: After silicon oxide film (9) is formed on the surface of a semiconductor substrate (1), the silicon oxide film (9) in a region in which a gate insulation film having a small effective thickness is formed is removed using diluted HF and after that, high dielectric constant insulation film (10) is formed on the semiconductor substrate (1). Consequently, two kinds of gate insulation films, namely, a gate insulation film (12) comprised of stacked film of high dielectric constant insulation film (10) and silicon oxide film (9) and gate insulation film (11) comprised of the high dielectric constant insulation film (10) are formed on the semiconductor substrate (1).

Abstract translation: 在半导体基板（1）的表面上形成氧化硅膜（9）之后，使用稀释的HF除去形成有效厚度小的栅极绝缘膜的区域中的氧化硅膜（9） 在半导体衬底（1）上形成高介电常数绝缘膜（10）。 因此，由高介电常数绝缘膜（10）和氧化硅膜（9）构成的栅极绝缘膜（12）和栅极绝缘膜（12）构成的两种栅极绝缘膜由高介电常数 在半导体衬底（1）上形成恒定绝缘膜（10）。

公开(公告)号：US07791962B2

公开(公告)日：2010-09-07

申请号：US12213131

申请日：2008-06-16

Applicant: Hideyuki Noda ,  Kazunori Saitoh ,  Kazutami Ariomoto ,  Katsumi Dosaka

Inventor： Hideyuki Noda ,  Kazunori Saitoh ,  Kazutami Ariomoto ,  Katsumi Dosaka

IPC: G11C7/10

CPC classification number: G11C7/1006

Abstract: A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.

Abstract translation: 存储单元垫被分成多个条目，并且对应于每个条目布置了算术逻辑单元。 在条目和相应的算术逻辑单元之间，以比特串行和并行方式执行算术/逻辑运算。 在并行操作不是非常有效的情况下，数据以串行和位并行方式传送到设置在存储器垫的下部的一组处理器。 以这种方式，无论操作内容或数据位宽度如何，都可以高速处理大量的数据。

公开(公告)号：US20100220531A1

公开(公告)日：2010-09-02

申请号：US12775377

申请日：2010-05-06

Applicant: YUTAKA SHINAGAWA ,  Takeshi Kataoka ,  Eiichi Ishikawa ,  Toshihiro Tanaka ,  Kazumasa Yanagisawa ,  Kazufumi Suzukawa

Inventor： YUTAKA SHINAGAWA ,  Takeshi Kataoka ,  Eiichi Ishikawa ,  Toshihiro Tanaka ,  Kazumasa Yanagisawa ,  Kazufumi Suzukawa

IPC: G11C16/04 ,  G06F12/02 ,  G06F11/00 ,  G06F13/20

CPC classification number: G11C16/349 ,  G11C16/06 ,  G11C16/3495

Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more.

Abstract translation: 半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写的非易失性存储区域。 非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。 第一非易失性存储区具有用于存储大于第二非易失性存储区的信息的阈值电压的最大变化宽度。 当用于存储信息的阈值电压的最大变化幅度较大时，由于由于存储信息的重写操作而对存储单元的应力变大，所以在保证重写操作次数方面较差; 然而，由于读取电流变大，因此可以加快存储器信息的读取速度。 可以优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以对第二非易失性存储器区域进行优先排列以保证存储器信息的重写操作的次数更多。

公开(公告)号：US20100214834A1

公开(公告)日：2010-08-26

申请号：US12772910

申请日：2010-05-03

Applicant: Hideto HIDAKA

Inventor： Hideto HIDAKA

IPC: G11C11/14 ,  G11C11/416

CPC classification number: G11C7/12 ,  G11C7/14 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C2207/002

Abstract: In the data read operation, a memory cell and a dummy memory cell are respectively coupled to two bit lines of a selected bit line pair, a data read current is supplied. In the selected memory cell column, a read gate drives the respective voltages on a read data bus pair, according to the respective voltages on the bit lines. A data read circuit amplifies the voltage difference between the read data buses so as to output read data. The use of the read gate enables the read data buses to be disconnected from a data read current path. As a result, respective voltage changes on the bit lines are rapidly produced, and therefore, the data read speed can be increased.

Abstract translation: 在数据读取操作中，存储器单元和虚拟存储单元分别耦合到所选位线对的两个位线，提供数据读取电流。 在选择的存储单元列中，根据位线上的相应电压，读取门驱动读取数据总线对上的相应电压。 数据读取电路放大读取数据总线之间的电压差，以输出读取数据。 读取门的使用使读取数据总线能够与数据读取当前路径断开连接。 结果，快速地产生位线上的各个电压变化，因此可以提高数据读取速度。