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    Method for manufacturing a semiconductor device including a silicon film
    1.
    发明授权
    Method for manufacturing a semiconductor device including a silicon film 有权
    包括硅膜的半导体器件的制造方法

    公开(公告)号：US07928014B2

    公开(公告)日：2011-04-19

    申请号：US11812423

    申请日：2007-06-19

    Applicant: Satoshi Ogino

    Inventor： Satoshi Ogino

    IPC: H01L21/302 ,  H01L21/461

    CPC classification number: H01L21/32137 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/28273 ,  H01L21/31116 ,  H01L21/32139 ,  H01L2924/0002 ,  Y10S438/905 ,  H01L2924/00

    Abstract: A method for manufacturing a semiconductor device includes: mounting a wafer having an exposed silicon nitride film, on an electrode received in a plasma chamber; dry-cleaning the chamber to remove reaction products accumulated on the wall and ceiling of the chamber, anisotropic-etching the silicon nitride film and an underlying silicon film for patterning; and removing the wafer from the chamber. The method repeats the treatment for a number of semiconductor wafers.

    Abstract translation: 一种半导体器件的制造方法，其特征在于，包括：将具有暴露的氮化硅膜的晶片安装在等离子体室中的电极上; 干燥室以除去积聚在室壁和天花板上的反应产物，各向异性蚀刻氮化硅膜和下层硅膜用于图案化; 并从该腔室中取出晶片。 该方法重复对多个半导体晶片的处理。

    Plasma reactor and method
    2.
    发明授权
    Plasma reactor and method 失效
    等离子体反应器和方法

    公开(公告)号：US06471821B2

    公开(公告)日：2002-10-29

    申请号：US08848881

    申请日：1997-05-01

    Applicant: Satoshi Ogino ,  Takahiro Maruyama

    Inventor： Satoshi Ogino ,  Takahiro Maruyama

    IPC: C23C1600

    CPC classification number: H01J37/32192 ,  H01J37/32678 ,  H01J37/32706 ,  H01L21/3065

    Abstract: A plasma reactor is provided for achieving extension of etching parameters to reduce charge-up shape anomaly and to improve selectivity, uniformity and workability in a dry etching process. An RF power fluctuates in cycles, each one of the cycles including first and second subcycles (25), (26) with different frequencies. The RF power in the first subcycles (25) is higher in frequency than that in the second subcycles (26). A charge accumulated during the first subcycles (25) in which the RF power of high frequency is applied can be relieved during the second subcycles (26) in which the RF power of low frequency is applied. At the same time, deterioration in an etching rate occurring with the application of only the RF power of low frequency can be relieved by applying the RF power of high frequency during the first subcycles (25).

    Abstract translation: 提供等离子体反应器用于实现蚀刻参数的延伸以减少电荷形状异常并提高干蚀刻工艺中的选择性，均匀性和可加工性。 RF功率以周期波动，每个周期包括具有不同频率的第一和第二子周期（25），（26）。 第一子周期（25）中的RF功率的频率高于第二子周期（26）。 在施加低频的RF功率的第二子周期（26）期间，可以释放在施加高频的RF功率的第一子周期（25）期间累积的电荷。 同时，通过在第一次循环（25）期间施加高频的RF功率，可以减轻仅施加低频的RF功率而发生的蚀刻速率的劣化。

    Plasma reactor
    3.
    发明授权
    Plasma reactor 失效
    等离子体反应器

    公开(公告)号：US06656849B2

    公开(公告)日：2003-12-02

    申请号：US10228999

    申请日：2002-08-28

    Applicant: Satoshi Ogino ,  Takahiro Maruyama

    Inventor： Satoshi Ogino ,  Takahiro Maruyama

    IPC: H01L21461

    CPC classification number: H01J37/32192 ,  H01J37/32678 ,  H01J37/32706 ,  H01L21/3065

    Abstract: A plasma reactor is provided for achieving extension of etching parameters to reduce charge-up shape anomaly and to improve selectivity, uniformity and workability in a dry etching process. An RF power fluctuates in cycles, each one of the cycles including first and second subcycles (25), (26) with different frequencies. The RF power in the first subcycles (25) is higher in frequency than that in the second subcycles (26). A charge accumulated during the first subcycles (25) in which the RF power of high frequency is applied can be relieved during the second subcycles (26) in which the RF power of low frequency is applied. At the same time, deterioration in an etching rate occurring with the application of only the RF power of low frequency can be relieved by applying the RF power of high frequency during the first subcycles (25).

    Abstract translation: 提供等离子体反应器用于实现蚀刻参数的延伸以减少电荷形状异常并提高干蚀刻工艺中的选择性，均匀性和可加工性。 RF功率以周期波动，每个周期包括具有不同频率的第一和第二子周期（25），（26）。 第一子周期（25）中的RF功率的频率高于第二子周期（26）。 在施加低频的RF功率的第二子周期（26）期间，可以释放在施加高频的RF功率的第一子周期（25）期间累积的电荷。 同时，通过在第一次循环（25）期间施加高频的RF功率，可以减轻仅施加低频的RF功率而发生的蚀刻速率的劣化。

    Semiconductor device and method of manufacturing same
    6.
    发明授权
    Semiconductor device and method of manufacturing same 有权
    半导体装置及其制造方法

    公开(公告)号：US08338247B2

    公开(公告)日：2012-12-25

    申请号：US12720174

    申请日：2010-03-09

    Applicant: Tadashi Yamaguchi ,  Toshiaki Tsutsumi ,  Satoshi Ogino ,  Kazumasa Yonekura ,  Kenji Kawai ,  Yoshihiro Miyagawa ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Kotaro Kihara

    Inventor： Tadashi Yamaguchi ,  Toshiaki Tsutsumi ,  Satoshi Ogino ,  Kazumasa Yonekura ,  Kenji Kawai ,  Yoshihiro Miyagawa ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Kotaro Kihara

    IPC: H01L27/092 ,  H01L21/8238

    CPC classification number: H01L21/823835 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7843

    Abstract: To improve the performance of semiconductor devices. Over an n+-type semiconductor region for source/drain of an n-channel type MISFET and a first gate electrode, and over a p+-type semiconductor region for source/drain of a p-channel type MISFET and a second gate electrode, which are formed over a semiconductor substrate, a metal silicide layer including nickel platinum silicide is formed by a salicide process. After that, a tensile stress film is formed over the whole face of the semiconductor substrate, and then the tensile stress film over the p-channel type MISFET is removed by dry-etching, and, after a compression stress film is formed over the whole face of the semiconductor substrate, the compression stress film over the n-channel type MISFET is removed by dry-etching. The Pt concentration in the metal silicide layer is highest at the surface, and becomes lower as the depth from the surface increases.

    Abstract translation: 提高半导体器件的性能。 在用于n沟道型MISFET和第一栅电极的源极/漏极的n +型半导体区域上，以及用于p沟道型MISFET和第二栅电极的源极/漏极的p +型半导体区域上，其中 形成在半导体衬底上，通过自对准硅化物工艺形成包括镍铂硅化物的金属硅化物层。 之后，在半导体基板的整个面上形成拉伸应力膜，然后通过干法蚀刻去除p沟道型MISFET上的拉伸应力膜，并且在整个压电应力膜形成之后 在半导体衬底的表面上，通过干蚀刻去除n沟道型MISFET上的压缩应力膜。 金属硅化物层中的Pt浓度在表面处最高，并且随着从表面的深度增加而变低。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20100230761A1

    公开(公告)日：2010-09-16

    申请号：US12720174

    申请日：2010-03-09

    Applicant: Tadashi Yamaguchi ,  Toshiaki Tsutsumi ,  Satoshi Ogino ,  Kazumasa Yonekura ,  Kenji Kawai ,  Yoshihiro Miyagawa ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Kotaro Kihara

    Inventor： Tadashi Yamaguchi ,  Toshiaki Tsutsumi ,  Satoshi Ogino ,  Kazumasa Yonekura ,  Kenji Kawai ,  Yoshihiro Miyagawa ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Kotaro Kihara

    IPC: H01L27/092 ,  H01L21/8238

    CPC classification number: H01L21/823835 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7843

    Abstract: To improve the performance of semiconductor devices. Over an n+-type semiconductor region for source/drain of an n-channel type MISFET and a first gate electrode, and over a p+-type semiconductor region for source/drain of a p-channel type MISFET and a second gate electrode, which are formed over a semiconductor substrate, a metal silicide layer including nickel platinum silicide is formed by a salicide process. After that, a tensile stress film is formed over the whole face of the semiconductor substrate, and then the tensile stress film over the p-channel type MISFET is removed by dry-etching, and, after a compression stress film is formed over the whole face of the semiconductor substrate, the compression stress film over the n-channel type MISFET is removed by dry-etching. The Pt concentration in the metal silicide layer is highest at the surface, and becomes lower as the depth from the surface increases.

    Abstract translation: 提高半导体器件的性能。 在用于n沟道型MISFET和第一栅电极的源极/漏极的n +型半导体区域上，以及用于p沟道型MISFET和第二栅电极的源极/漏极的p +型半导体区域上，其中 形成在半导体衬底上，通过自对准硅化物工艺形成包括镍铂硅化物的金属硅化物层。 之后，在半导体基板的整个面上形成拉伸应力膜，然后通过干法蚀刻去除p沟道型MISFET上的拉伸应力膜，并且在整个压电应力膜形成之后 在半导体衬底的表面上，通过干蚀刻去除n沟道型MISFET上的压缩应力膜。 金属硅化物层中的Pt浓度在表面处最高，并且随着从表面的深度增加而变低。

    Method for manufacturing a semiconductor device including a silicon film
    9.
    发明申请
    Method for manufacturing a semiconductor device including a silicon film 有权
    包括硅膜的半导体器件的制造方法

    公开(公告)号：US20070293051A1

    公开(公告)日：2007-12-20

    申请号：US11812423

    申请日：2007-06-19

    Applicant: Satoshi Ogino

    Inventor： Satoshi Ogino

    IPC: H01L21/302

    CPC classification number: H01L21/32137 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/28273 ,  H01L21/31116 ,  H01L21/32139 ,  H01L2924/0002 ,  Y10S438/905 ,  H01L2924/00

    Abstract: A method for manufacturing a semiconductor device includes: mounting a wafer having an exposed silicon nitride film, on an electrode received in a plasma chamber; dry-cleaning the chamber to remove reaction products accumulated on the wall and ceiling of the chamber, anisotropic-etching the silicon nitride film and an underlying silicon film for patterning; and removing the wafer from the chamber. The method repeats the treatment for a number of semiconductor wafers.

    Abstract translation: 一种半导体器件的制造方法，其特征在于，包括：将具有暴露的氮化硅膜的晶片安装在等离子体室中的电极上; 干燥室以除去积聚在室壁和天花板上的反应产物，各向异性蚀刻氮化硅膜和下层硅膜用于图案化; 并从该腔室中取出晶片。 该方法重复对多个半导体晶片的处理。

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