公开(公告)号：US06452226B2

公开(公告)日：2002-09-17

申请号：US09790700

申请日：2001-02-23

Applicant: Kenji Kawai ,  Hajime Kimura ,  Kazuyuki Ohmi

Inventor： Kenji Kawai ,  Hajime Kimura ,  Kazuyuki Ohmi

IPC: H01L2972

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

Abstract: A non-volatile semiconductor memory device and a manufacturing method of the same where an etching residue generating short-circuit between gates is made harmless or a device is miniaturized are obtained. The method includes the steps of forming on a semiconductor substrate, a first gate layer and a second gate layer, forming a second gate electrode by etching the second gate layer, forming a first gate electrode by etching the first gate layer using the second gate electrode as a mask, and removing a residue left on a step portion by isotropic etching.

Abstract translation: 获得了非易失性半导体存储器件及其制造方法，其中在栅极之间产生短路的蚀刻残留变得无害或器件小型化。 该方法包括以下步骤：在半导体衬底上形成第一栅极层和第二栅极层，通过蚀刻第二栅极层形成第二栅电极，通过使用第二栅电极蚀刻第一栅极层来形成第一栅电极 作为掩模，并通过各向同性蚀刻除去残留在台阶部分上的残留物。

公开(公告)号：US06346482B2

公开(公告)日：2002-02-12

申请号：US09176878

申请日：1998-10-21

Applicant: Junko Matsumoto ,  Shigenori Sakamori ,  Akemi Teratani ,  Yoshihiro Kusumi ,  Tetsuhiro Fukao ,  Kazuyuki Ohmi ,  Kanji Tabaru ,  Nobuaki Yamanaka

Inventor： Junko Matsumoto ,  Shigenori Sakamori ,  Akemi Teratani ,  Yoshihiro Kusumi ,  Tetsuhiro Fukao ,  Kazuyuki Ohmi ,  Kanji Tabaru ,  Nobuaki Yamanaka

IPC: H01L21302

CPC classification number: H01L21/76897 ,  H01L21/31116 ,  H01L21/76802

Abstract: There is described formation of a contact hole without involvement of damage to an etching stopper film and deterioration of electric characteristics, achieved by means of a self-alignment method. An interlayer oxide film is etched through an opening of a resist mask, and by means of plasma etching through use of a processing gas comprising a mixture of a rare gas and a CF-based gas, thereby tapering a shoulder of the silicon nitride film. Alternatively, a silicon oxide film and a silicon nitride film are continually etched through an opening of the resist mask, by means of plasma etching through use of a CH2F2 gas added to a mixed gas including a rare gas and a C4F8 gas.

Abstract translation: 描述了通过自对准方法实现的接触孔的形成，而不涉及对蚀刻阻挡膜的损伤和电特性的劣化。 通过抗蚀剂掩模的开口蚀刻层间氧化膜，并且通过使用包含稀有气体和CF基气体的混合物的处理气体的等离子体蚀刻，从而使氮化硅膜的台肩逐渐变细。 或者，通过使用添加到包括稀有气体和C 4 F 8气体的混合气体中的CH 2 F 2气体的等离子体蚀刻，通过抗蚀剂掩模的开口，连续蚀刻氧化硅膜和氮化硅膜。

公开(公告)号：US06232209B1

公开(公告)日：2001-05-15

申请号：US09440568

申请日：1999-11-15

Applicant: Nobuo Fujiwara ,  Takahiro Maruyama ,  Shigenori Sakamori ,  Akemi Teratani ,  Satoshi Ogino ,  Kazuyuki Ohmi ,  Yuzo Irie

Inventor： Nobuo Fujiwara ,  Takahiro Maruyama ,  Shigenori Sakamori ,  Akemi Teratani ,  Satoshi Ogino ,  Kazuyuki Ohmi ,  Yuzo Irie

IPC: H01L213205

CPC classification number: H01L21/28114 ,  H01L21/28044 ,  H01L21/32137 ,  H01L29/42376 ,  H01L29/4941

Abstract: A gate electrode includes a polycrystalline silicon layer, a barrier layer and a metal layer. The metal layer and barrier layer includes for example W and RuO2 layers, respectively. In forming the gate electrode, the metal layer and barrier layer are etched using at least one of the barrier layer and polycrystalline silicon layer as an etching stopper.

Abstract translation: 栅电极包括多晶硅层，阻挡层和金属层。 金属层和阻挡层分别包括例如W和RuO 2层。 在形成栅电极时，使用阻挡层和多晶硅层中的至少一个作为蚀刻停止层蚀刻金属层和阻挡层。

公开(公告)号：US07173553B2

公开(公告)日：2007-02-06

申请号：US11235334

申请日：2005-09-27

Applicant: Kazuyuki Ohmi ,  Kenichi Tatehara

Inventor： Kazuyuki Ohmi ,  Kenichi Tatehara

IPC: H03M1/66

CPC classification number: H03M1/687 ,  H03M1/747 ,  H03M1/785

Abstract: A current summing type D/A converter having a configuration of two or more steps is provided. In a D/A converter block of the first step, by adding current segments, upper bits are D/A converted, and one of the current segments in the first step is further supplied to a D/A converter block in a second step to be shunt by the D/A converter block in the second step, so that lower bits are D/A converted. The output current in the first step and the output current in the second step are then added each other. According to the foregoing method, the D/A conversion may be performed without causing a differential linearity error.

Abstract translation: 提供具有两个或多个步骤的配置的电流求和型D / A转换器。 在第一步的D / A转换器模块中，通过加上当前段，高位进行D / A转换，第一步中的当前段之一进一步提供给D / A转换器模块， 在第二步中由D / A转换器模块分流，以便低位转换为D / A。 然后将第一步骤中的输出电流和第二步骤中的输出电流相加。 根据上述方法，可以执行D / A转换而不引起差分线性误差。

公开(公告)号：US20060114142A1

公开(公告)日：2006-06-01

申请号：US11235334

申请日：2005-09-27

Applicant: Kazuyuki Ohmi ,  Kenichi Tatehara

Inventor： Kazuyuki Ohmi ,  Kenichi Tatehara

IPC: H03M1/12

CPC classification number: H03M1/687 ,  H03M1/747 ,  H03M1/785

Abstract: A current summing type D/A converter having a configuration of two or more steps is provided. In a D/A converter block of the first step, by adding current segments, upper bits are D/A converted, and one of the current segments in the first step is further supplied to a D/A converter block in a second step to be shunt by the D/A converter block in the second step, so that lower bits are D/A converted. The output current in the first step and the output current in the second step are then added each other. According to the foregoing method, the D/A conversion may be performed without causing a differential linearity error.

Abstract translation: 提供具有两个或多个步骤的配置的电流求和型D / A转换器。 在第一步骤的D / A转换器模块中，通过加上当前段，高位进行D / A转换，第一步中的当前段之一进一步提供给D / A转换器模块， 在第二步中由D / A转换器模块分流，以便低位转换为D / A。 然后将第一步骤中的输出电流和第二步骤中的输出电流相加。 根据上述方法，可以执行D / A转换而不引起差分线性误差。

公开(公告)号：US06783274B2

公开(公告)日：2004-08-31

申请号：US10391592

申请日：2003-03-20

Applicant: Takehiko Umeyama ,  Kazuyuki Ohmi

Inventor： Takehiko Umeyama ,  Kazuyuki Ohmi

IPC: G01K701

CPC classification number: G01K7/01

Abstract: A device for measuring temperature of a semiconductor integrated circuit includes first and second current mirror circuits, an N channel transistor connected to an output terminal of the second cur rent mirror circuit, an npn transistor connected to an output terminal of the first current mirror circuit and the N channel transistor, and an operational transistor connected to a node between the second current circuit and the N channel transistor. Currents that flow from the second current mirror circuit to the N channel transistor and from the N channel transistor to the npn transistor have different temperature coefficients. The operational amplifier corrects the difference in the temperature coefficients of these currents to output a voltage of ground electric potential standard.

Abstract translation: 用于测量半导体集成电路的温度的装置包括第一和第二电流镜电路，连接到第二电流镜电路的输出端的N沟道晶体管，连接到第一电流镜电路的输出端的npn晶体管， N沟道晶体管和连接到第二电流电路和N沟道晶体管之间的节点的工作晶体管。 从第二电流镜电路流向N沟道晶体管，从N沟道晶体管流向npn晶体管的电流具有不同的温度系数。 运算放大器校正这些电流的温度系数的差异，以输出地电位标准电压。

公开(公告)号：US06228712B1

公开(公告)日：2001-05-08

申请号：US09286421

申请日：1999-04-06

Applicant: Kenji Kawai ,  Hajime Kimura ,  Kazuyuki Ohmi

Inventor： Kenji Kawai ,  Hajime Kimura ,  Kazuyuki Ohmi

IPC: H01L2972

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

Abstract: A non-volatile semiconductor memory device and a manufacturing method of the same where an etching residue generating short-circuit between gates is made harmless or a device is miniaturized are obtained. The method includes the steps of forming on a semiconductor substrate, a first gate layer and a second gate layer, forming a second gate electrode by etching the second gate layer, forming a first gate electrode by etching the first gate layer using the second gate electrode as a mask, and removing a residue left on a step portion by isotropic etching.