公开(公告)号：US20100229161A1

公开(公告)日：2010-09-09

申请号：US12694657

申请日：2010-01-27

Applicant: Noriyasu MORI

Inventor： Noriyasu MORI

IPC: G06F9/45

CPC classification number: G06F8/456

Abstract: A compile technique is provided for multicore allocation, by which a desired running performance can be achieved. The steps of analyzing a taskization directive, taskizing a specified part, and assigning a specified CPU the task are adopted for the compile technique. According to the program-to-tasks-decomposition compile technique, the multicore decomposition is performed by allocating tasks to CPUs individually while following a task decomposition directive of a main part designated by a user. When no direction is issued concerning a CPU to be allocated, the relation with a principal task is judged from the relation of invocation and the dependency, and CPU to be allocated, and then the CPU to be allocated is determined. In allocation to the CPU, an efficient multicore-task decomposition is achieved in consideration of copy and assignment of one processing to more than one CPU while figuring in the balance between processing speed and resources.

Abstract translation: 提供了一种用于多核分配的编译技术，通过该编译技术可以实现期望的运行性能。 为编译技术采用分析任务指令，指定部分任务以及分配指定CPU任务的步骤。 根据程序到任务分解编译技术，通过在根据用户指定的主要部分的任务分解指令之后单独分配任务来执行多核分解。 当没有关于要分配的CPU的方向发布时，根据调用和依赖关系以及要分配的CPU来判断与主任务的关系，然后确定要分配的CPU。 在分配给CPU时，考虑到将一个处理复制和分配给多个CPU，同时计算处理速度和资源之间的平衡，实现了高效的多核任务分解。

公开(公告)号：US5197131A

公开(公告)日：1993-03-23

申请号：US307501

申请日：1989-02-08

Applicant: Noriyasu Mori ,  Hiroshi Tomita

Inventor： Noriyasu Mori ,  Hiroshi Tomita

IPC: G06F9/38

CPC classification number: G06F9/3814 ,  G06F9/3804 ,  G06F9/381

Abstract: In an information processing system having an instruction buffer, an instruction buffer is controlled to primarily increase the instruction hit ratio of a sequence of instructions including a procedure-call instruction. In the first configuration, there is provided a mechanism which subdivides the instruction buffer into a plurality of instruction buffer banks so as to switch the instruction buffer bank to a current use in association with a dynamic procedure call, thereby improving the instruction hit ratio in the procedure call and in the return operation. In the second configuration, there are provided instruction words to subdivide and to control the instruction buffer such that the user can specify a method of controlling the instruction buffer. An instruction loop is captured efficiently and an arbitrary instruction sequence of a program is stored as a resident routine in the buffer so as to increase the instruction hit ratio.

Abstract translation: 在具有指令缓冲器的信息处理系统中，控制指令缓冲器以主要增加包括过程调用指令的指令序列的指令命中率。 在第一种配置中，提供了一种将指令缓冲器分成多个指令缓冲器组的机制，以便将指令缓冲器组与动态过程调用相关联地切换到当前使用，从而提高指令缓冲器组中的指令命中率 程序调用和返回操作。 在第二配置中，提供了指令字来细分和控制指令缓冲器，使得用户可以指定控制指令缓冲器的方法。 有效地捕获指令循环，并且将程序的任意指令序列作为驻留例程存储在缓冲器中，以增加指令命中率。

公开(公告)号：US5790877A

公开(公告)日：1998-08-04

申请号：US675033

申请日：1996-07-03

Applicant: Hiroyasu Nishiyama ,  Sumio Kikuchi ,  Noriyasu Mori ,  Akira Nishimoto ,  Yooichi Takeuchi

Inventor： Hiroyasu Nishiyama ,  Sumio Kikuchi ,  Noriyasu Mori ,  Akira Nishimoto ,  Yooichi Takeuchi

IPC: G06F15/78 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/32 ,  G06F9/30 ,  G06F9/38 ,  G06F9/45 ,  G06F1/00 ,  G06F1/18 ,  G06F1/26

CPC classification number: G06F9/30083 ,  G06F1/08 ,  G06F1/32 ,  G06F8/4432 ,  G06F9/3869 ,  Y02B60/181

Abstract: In a processor system including a plurality of hardware resources, a method for arranging a program to suppress the power consumption by the resources includes the steps of determining which ones of the hardware resources are to be operated and from which instruction cycle to which instruction cycle to execute each instruction of the program; and based on the determination, adding an instruction to lower frequencies of clock signals inputted to the hardware resources and an instruction to restore the frequency at positions adjacent to the beginning and the end of the period during which the hardware resources are not operated and compiling the program. The processor system decodes the compiled program and lowers the frequency of the clock signal inputted to the hardware resources in accordance with the frequency lowering instruction and the frequency restoring instruction detected in the decoding step. The clock signals sent to the hardware resources are stopped by the frequency lowering instruction to the resource of the hardware resources for which the clock frequency may be lowered to zero.

Abstract translation: 在包括多个硬件资源的处理器系统中，一种用于排列节目以消除资源的功率消耗的方法包括以下步骤：确定哪些硬件资源将被操作，以及从哪个指令周期到哪个指令周期 执行程序的每个指令; 并且基于该确定，向输入到硬件资源的时钟信号的较低频率添加指令，以及在硬件资源不被操作的周期的开始和结束的相邻位置处恢复频率的指令，并编译 程序。 处理器系统根据在解码步骤中检测到的频率降低指令和频率恢复指令，对编译的程序进行解码并降低输入到硬件资源的时钟信号的频率。 发送到硬件资源的时钟信号通过降频指令停止到时钟频率可以降低到零的硬件资源的资源。