公开(公告)号：US08769978B2

公开(公告)日：2014-07-08

申请号：US12593965

申请日：2008-03-28

Applicant: Takanobu Nakaguro ,  Toshihiro Tsuemoto ,  Hiroyuki Kakiuchi ,  Hideto Hidaka

Inventor： Takanobu Nakaguro ,  Toshihiro Tsuemoto ,  Hiroyuki Kakiuchi ,  Hideto Hidaka

IPC: F24F3/14

CPC classification number: F24F3/1411 ,  B60H3/024 ,  B60H2003/028 ,  B60H2003/0691 ,  F24F2221/34

Abstract: In a dehumidification/humidification device, a blower and an adsorbent module are contained in a casing. In other embodiment, the blower, the adsorbent module, and a flow passage-changing device are contained in the casing. The adsorbent module includes an adsorbing element formed by carrying an adsorbent on a permeable element and a heater directly disposed on the adsorbing element. The state of the electrification of the heater is changed and an air-blowing direction or a flow passage is changed, whereby a dehumidified air is discharged from a first suction/discharge port (or discharge port), and a humidified air is discharged from a second suction/discharge port (or discharge port).

Abstract translation: 在除湿/加湿装置中，鼓风机和吸附剂组件包含在壳体中。 在其他实施例中，鼓风机，吸附剂组件和流路改变装置包含在壳体中。 吸附剂组件包括通过在可渗透元件上承载吸附剂和直接设置在吸附元件上的加热器形成的吸附元件。 改变加热器的通电状态，改变送风方向或流路，从而从第一吸引排出口（或排出口）排出除湿空气，从空气排出 第二吸入口（或排出口）。

公开(公告)号：US08351253B2

公开(公告)日：2013-01-08

申请号：US13177301

申请日：2011-07-06

Applicant: Hideto Hidaka

Inventor： Hideto Hidaka

IPC: G11C11/14 ,  G11C11/15 ,  G11C11/00

CPC classification number: H01L27/228 ,  G11C7/14 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/224

Abstract: A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provided between the fixed and free magnetic layers in a tunnel junction region. In the free magnetic layer, a region corresponding to an easy axis region having characteristics desirable as a memory cell is used as the tunnel junction region. A hard axis region having characteristics undesirable as a memory cell is not used as a portion of the tunnel magnetic resistive element.

公开(公告)号：US07948795B2

公开(公告)日：2011-05-24

申请号：US12772910

申请日：2010-05-03

Applicant: Hideto Hidaka

Inventor： Hideto Hidaka

IPC: G11C11/15

CPC classification number: G11C7/12 ,  G11C7/14 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C2207/002

Abstract: In the data read operation, a memory cell and a dummy memory cell are respectively coupled to two bit lines of a selected bit line pair, a data read current is supplied. In the selected memory cell column, a read gate drives the respective voltages on a read data bus pair, according to the respective voltages on the bit lines. A data read circuit amplifies the voltage difference between the read data buses so as to output read data. The use of the read gate enables the read data buses to be disconnected from a data read current path. As a result, respective voltage changes on the bit lines are rapidly produced, and therefore, the data read speed can be increased.

Abstract translation: 在数据读取操作中，存储器单元和虚拟存储单元分别耦合到所选位线对的两个位线，提供数据读取电流。 在选择的存储单元列中，根据位线上的相应电压，读取门驱动读取数据总线对上的相应电压。 数据读取电路放大读取数据总线之间的电压差，以输出读取数据。 读取门的使用使读取数据总线能够与数据读取当前路径断开连接。 结果，快速地产生位线上的各个电压变化，因此可以提高数据读取速度。

公开(公告)号：US07885096B2

公开(公告)日：2011-02-08

申请号：US12481392

申请日：2009-06-09

Applicant: Hideto Hidaka

Inventor： Hideto Hidaka

IPC: G11C11/00 ,  G11C5/08 ,  G11C7/00

CPC classification number: G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

Abstract: An end of a selected bit line in a selected column is electrically coupled to an end of a corresponding current return line by one of first and second write column select gates, which are selectively turned on in response to results of column selection. A data write circuit sets the other end of the selected bit line and the other end of the current return line to one and the other of a power supply voltage and a ground voltage in accordance with a level of write data via one of first and second data buses and an inverted data bus, respectively.

Abstract translation: 所选列中的所选位线的一端通过第一和第二写列选择栅中的一个电耦合到对应的电流返回线的一端，这些选择栅根据列选择的结果选择性地导通。 数据写入电路根据写入数据的电平，将所选位线的另一端和当前返回线的另一端设置为电源电压和接地电压的另一端，经由第一和第二 数据总线和反相数据总线。

公开(公告)号：US07633827B2

公开(公告)日：2009-12-15

申请号：US12125733

申请日：2008-05-22

Applicant: Hideto Hidaka

Inventor： Hideto Hidaka

IPC: G11C11/00

CPC classification number: G11C11/005

Abstract: A thin film magnetic memory includes a size-variable Read Only Memory (ROM) region and a size-variable Random Access Memory (RAM) coupled to different ports for parallel access to the ports, respectively. A memory system allowing fast and efficient data transfer can be achieved.

Abstract translation: 薄膜磁存储器包括大小可变只读存储器（ROM）区域和耦合到不同端口的大小可变随机存取存储器（RAM），用于并行地访问端口。 可以实现快速高效的数据传输的存储器系统。

公开(公告)号：US07616476B2

公开(公告)日：2009-11-10

申请号：US11882577

申请日：2007-08-02

Applicant: Hideto Hidaka

Inventor： Hideto Hidaka

IPC: G11C11/00

CPC classification number: G11C11/16

Abstract: After a digit line is charged to a power supply voltage by turn-on of a first switching element, the first switching element is turned off and a second switching element is turned on, whereby the digit line is connected to a ground voltage. Similarly, in order to feed data write current, a bit line is charged to a data voltage in accordance with write data through a third switching element. Then, the bit line is connected to a voltage different from the data voltage by a fourth switching element while the third switching element is turned off. Therefore, a load current from a power supply to an MRAM device is supplied during charging of a digit line capacitance and a bit line capacitance, without being consumed when the data write current flows. Consequently, a peak of the load current supplied from the power supply is suppressed.

Abstract translation: 在通过第一开关元件的接通将数字线充电到电源电压之后，第一开关元件被断开并且第二开关元件导通，从而数字线连接到接地电压。 类似地，为了馈送数据写入电流，根据通过第三开关元件的写入数据将位线充电到数据电压。 然后，第三开关元件断开时，位线被第四开关元件连接到与数据电压不同的电压。 因此，在数字线电容和位线电容的充电期间，从电源到MRAM器件的负载电流被提供，而不会在数据写入电流流动时被消耗。 因此，抑制了从电源供给的负载电流的峰值。

公开(公告)号：US20090179692A1

公开(公告)日：2009-07-16

申请号：US12403830

申请日：2009-03-13

Applicant: Hideto HIDAKA

Inventor： Hideto HIDAKA

IPC: G05F1/10

CPC classification number: H03K19/0016

Abstract: Transistors having large gate tunnel barriers are used as transistors to be on in a standby state, MIS transistors having thin gate insulating films are used as transistors to be off in the standby state, and main and sub-power supply lines and main and sub-ground lines forming a hierarchical power supply structure are isolated from each other in the standby state so that a gate tunnel current is reduced in the standby state in which a low power consumption is required. In general, a gate tunnel current reducing mechanism is provided for any circuitry operating in a standby state and an active state, and is activated in the standby state to reduce the gate tunnel current in the circuitry in the standby state, to reduce power consumption in the standby state.

Abstract translation: 使用具有大栅极通道势垒的晶体管作为晶体管处于待机状态，具有薄栅极绝缘膜的MIS晶体管被用作在备用状态下关断的晶体管，以及主和副电源线以及主和副电源， 形成分层供电结构的接地线在待机状态下彼此隔离，使得在需要低功耗的待机状态下，栅极隧道电流减小。 通常，为处于待机状态和有效状态的任何电路提供栅极通道电流减小机构，并且在备用状态下被激活以减少处于待机状态的电路中的栅极隧道电流，从而降低功耗 待机状态。

公开(公告)号：US20090154225A1

公开(公告)日：2009-06-18

申请号：US12370989

申请日：2009-02-13

Applicant: Hideto HIDAKA

Inventor： Hideto HIDAKA

IPC: G11C11/02 ,  G11C11/416

CPC classification number: G11C5/025 ,  B82Y10/00 ,  G11C11/1653 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  H01L27/228

Abstract: Read word lines and write word lines are provided corresponding to the respective MTJ (Magnetic Tunnel Junction) memory cell rows, and bit lines and reference voltage lines are provided corresponding to the respective MTJ memory cell columns. Adjacent MTJ memory cells share at least one of these signal lines. As a result, the pitches of signal lines provided in the entire memory array can be widened. Thus, the MTJ memory cells can be efficiently arranged, achieving improved integration of the memory array.

Abstract translation: 对应于相应的MTJ（磁隧道结）存储单元行提供读字线和写字线，并且对应于相应的MTJ存储单元列提供位线和参考电压线。 相邻的MTJ存储器单元共享这些信号线中的至少一个。 结果，可以扩大设置在整个存储器阵列中的信号线的间距。 因此，可以有效地布置MTJ存储器单元，实现存储器阵列的改进的集成。

公开(公告)号：US07489001B2

公开(公告)日：2009-02-10

申请号：US11708030

申请日：2007-02-20

Applicant: Hideto Hidaka

Inventor： Hideto Hidaka

IPC: H01L27/108

CPC classification number: H01L27/228 ,  G11C8/08 ,  G11C11/15 ,  G11C11/16

Abstract: An MTJ memory cell is independently provided with a write word line and a read word line used for data write and data read. By separately arranging read word lines every two regions formed by dividing a memory array in the column direction, it is possible to reduce signal propagation delays of the read word lines and accelerate the data read operation. Activation of each read word line is controlled by a write word line in accordance with a row selection result in a hierarchical manner. A word-line-current control circuit forms and cuts off the current path of a write word line correspondingly to data write and data read.

Abstract translation: MTJ存储单元独立地具有用于数据写入和数据读取的写字线和读字线。 通过在列方向上划分存储器阵列形成的每两个区域分开布置读取字线，可以减少读取的字线的信号传播延迟并加速数据读取操作。 每个读取字线的激活根据分层方式的行选择结果由写入字线控制。 字线电流控制电路对应于数据写入和数据读取形成并切断写入字线的当前路径。

公开(公告)号：US20080239795A1

公开(公告)日：2008-10-02

申请号：US12133519

申请日：2008-06-05

Applicant: Tsukasa OOISHI ,  Hideto Hidaka

Inventor： Tsukasa OOISHI ,  Hideto Hidaka

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C11/16

Abstract: A data write current from a pinned layer to a free layer is larger than a data write current from the free layer to the pinned layer. A data read current is smaller in value than the data write current. In the case where a difference in data read current between a high-resistance state and a low-resistance state is relatively small, a sense amplifier is connected so that the data read current flows from the pinned layer to the free layer, namely from a source line to a bit line.

Abstract translation: 从固定层到自由层的数据写入电流大于从自由层到被钉扎层的数据写入电流。 数据读取电流的值比数据写入电流小。 在高电阻状态和低电阻状态之间的数据读取电流的差异相对较小的情况下，连接读出放大器，使得数据读取电流从固定层流向自由层，即从 源线到位线。