公开(公告)号：US20240387276A1

公开(公告)日：2024-11-21

申请号：US18787901

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Chien-Hao Chen ,  Ching-Hwanq Su

IPC: H01L21/8234 ,  H01L27/088

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.

公开(公告)号：US20240243190A1

公开(公告)日：2024-07-18

申请号：US18622230

申请日：2024-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ching-Hwanq Su ,  Pin Chia Su ,  Ying Hsin Lu ,  I-Shan Huang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/7851

Abstract: A method includes forming a dummy gate stack over a fin protruding from a semiconductor substrate, forming gate spacers on sidewalls of the dummy gate stack, forming source/features over portions of the fin, forming a gate trench between the gate spacers, which includes trimming top portions of the gate spacers to form a funnel-like opening in the gate trench, and forming a metal gate structure in the gate trench. A semiconductor structure includes a fin protruding from a substrate, a metal gate structure disposed over the fin, gate spacers disposed on sidewalls of the metal gate structure, where a top surface of each gate spacer is angled toward the semiconductor fin, a dielectric layer disposed over the top surface of each gate spacer, and a conductive feature disposed between the gate spacers to contact the metal gate structure, where sidewalls of the conductive feature contact the dielectric layer.

公开(公告)号：US11855098B2

公开(公告)日：2023-12-26

申请号：US17986379

申请日：2022-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yen Tsai ,  Ming-Chi Huang ,  Zoe Chen ,  Wei-Chin Lee ,  Cheng-Lung Hung ,  Da-Yuan Lee ,  Weng Chang ,  Ching-Hwanq Su

IPC: H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H01L27/092 ,  H01L21/324 ,  H01L29/08 ,  H01L21/768 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/10 ,  H01L21/321 ,  H01L21/027 ,  H01L29/49

CPC classification number: H01L27/0924 ,  H01L21/0228 ,  H01L21/0271 ,  H01L21/02318 ,  H01L21/02321 ,  H01L21/28088 ,  H01L21/324 ,  H01L21/3212 ,  H01L21/76829 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/517 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7851 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/7848

Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.

公开(公告)号：US20230335601A1

公开(公告)日：2023-10-19

申请号：US18341486

申请日：2023-06-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Ya-Huei Li ,  Da-Yuan Lee ,  Ching-Hwanq Su

IPC: H01L29/40 ,  H01L27/088 ,  H01L21/3215 ,  H01L21/8234 ,  H01L21/285 ,  H01L29/49

CPC classification number: H01L29/401 ,  H01L27/0886 ,  H01L21/3215 ,  H01L21/823437 ,  H01L21/28568 ,  H01L29/4966

Abstract: A method includes forming a gate dielectric comprising a portion extending on a semiconductor region, forming a barrier layer comprising a portion extending over the portion of the gate dielectric, forming a work function tuning layer comprising a portion over the portion of the barrier layer, doping a doping element into the work function tuning layer, removing the portion of the work function tuning layer, thinning the portion of the barrier layer, and forming a work function layer over the portion of the barrier layer.

公开(公告)号：US20230207650A1

公开(公告)日：2023-06-29

申请号：US18171128

申请日：2023-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ying Hsin Lu ,  Ching-Hwanq Su ,  Pin Chia Su ,  Ling-Sung Wang

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/786 ,  H01L29/40

CPC classification number: H01L29/42376 ,  H01L27/088 ,  H01L29/404 ,  H01L29/42392 ,  H01L29/78696

Abstract: The present disclosure provides a semiconductor structure in accordance with some embodiment. The semiconductor structure includes a semiconductor substrate having a first circuit region and a second circuit region; active regions extended from the semiconductor substrate and surrounded by isolation features; first transistors that include first gate stacks formed on the active regions and disposed in the first circuit region, the first gate stacks having a first gate pitch less than a reference pitch; and second transistors that include second gate stacks formed on the active regions and disposed in the second circuit region, the second gate stacks having a second pitch greater than the reference pitch. The second transistors are high-frequency transistors and the first transistors are logic transistors.

公开(公告)号：US11563120B2

公开(公告)日：2023-01-24

申请号：US17077383

申请日：2020-10-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Chia-Ching Lee ,  Chung-Chiang Wu ,  Ching-Hwanq Su

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51

Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.

公开(公告)号：US20220216317A1

公开(公告)日：2022-07-07

申请号：US17700172

申请日：2022-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ching-Hwanq Su ,  Pohan Kung ,  Ying Hsin Lu ,  I-Shan Huang

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a channel component of a transistor and a gate component disposed over the channel component. The gate component includes: a dielectric layer, a first work function metal layer disposed over the dielectric layer, a fill-metal layer disposed over the first work function metal layer, and a second work function metal layer disposed over the fill-metal layer.

公开(公告)号：US11322411B2

公开(公告)日：2022-05-03

申请号：US16686408

申请日：2019-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yen Tsai ,  Chung-Chiang Wu ,  Tai-Wei Hwang ,  Hung-Chin Chung ,  Wei-Chin Lee ,  Da-Yuan Lee ,  Ching-Hwanq Su ,  Yin-Chuan Chuang ,  Kuan-Ting Liu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/02 ,  H01L29/51

Abstract: Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers.

公开(公告)号：US11222818B2

公开(公告)日：2022-01-11

申请号：US16034843

申请日：2018-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiang Chao ,  Min-Hsiu Hung ,  Chun-Wen Nieh ,  Ya-Huei Li ,  Yu-Hsiang Liao ,  Li-Wei Chu ,  Kan-Ju Lin ,  Kuan-Yu Yeh ,  Chi-Hung Chuang ,  Chih-Wei Chang ,  Ching-Hwanq Su ,  Hung-Yi Huang ,  Ming-Hsing Tsai

IPC: H01L23/00 ,  H01L21/768 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/45 ,  H01L21/324 ,  H01L29/66 ,  H01L21/285 ,  H01L21/265 ,  H01L23/535

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure, and the epitaxial structure is adjacent to the gate stack. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes applying a metal-containing material on the epitaxial structure while the epitaxial structure is heated so that a portion of the epitaxial structure is transformed to form a metal-semiconductor compound region.

公开(公告)号：US20210305386A1

公开(公告)日：2021-09-30

申请号：US17175368

申请日：2021-02-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ying Hsin Lu ,  Ching-Hwanq Su ,  Pin Chia Su ,  Ling-Sung Wang

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/40 ,  H01L29/786

Abstract: The present disclosure provides a semiconductor structure in accordance with some embodiment. The semiconductor structure includes a semiconductor substrate having a first circuit region and a second circuit region; active regions extended from the semiconductor substrate and surrounded by isolation features; first transistors that include first gate stacks formed on the active regions and disposed in the first circuit region, the first gate stacks having a first gate pitch less than a reference pitch; and second transistors that include second gate stacks formed on the active regions and disposed in the second circuit region, the second gate stacks having a second pitch greater than the reference pitch. The second transistors are high-frequency transistors and the first transistors are logic transistors.