公开(公告)号：US10090213B2

公开(公告)日：2018-10-02

申请号：US15449683

申请日：2017-03-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzuan-Horng Liu ,  Chen-Hua Yu ,  Hsien-Pin Hu ,  Tzu-Yu Wang ,  Wei-Cheng Wu ,  Shang-Yun Hou ,  Shin-Puu Jeng

IPC: H01L21/48 ,  H01L21/66 ,  H01L23/498 ,  H01L23/58 ,  G01R1/073

Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.

公开(公告)号：US20180218989A1

公开(公告)日：2018-08-02

申请号：US15935811

申请日：2018-03-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Hsien Hsieh ,  Hsien-Wei Chen ,  Chen-Hua Yu ,  Tsung-Shu Lin ,  Wei-Cheng Wu

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/05 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/562 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/35121 ,  H01L2924/00012

Abstract: A redistribution layer with a landing pad is formed over a substrate with one or more mesh holes extending through the landing pad. The mesh holes may be arranged in a circular shape, and a passivation layer may be formed over the landing pad and the mesh holes. An opening is formed through the passivation layer and an underbump metallization is formed in contact with an exposed portion of the landing pad and extends over the mesh holes. By utilizing the mesh holes, sidewall delamination and peeling that might otherwise occur may be reduced or eliminated.

公开(公告)号：US09997464B2

公开(公告)日：2018-06-12

申请号：US15225024

申请日：2016-08-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Wei-Cheng Wu ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L23/5386 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An embodiment device includes an integrated circuit die and a first metallization pattern over the integrated circuit die. The first metallization pattern includes a first dummy pattern having a first hole extending through a first conductive region. The device further includes a second metallization pattern over the first metallization pattern. The second metallization pattern includes a second dummy pattern having a second hole extending through a second conductive region. The second hole is arranged projectively overlapping a portion of the first hole and a portion of the first conductive region.

公开(公告)号：US09929112B2

公开(公告)日：2018-03-27

申请号：US14865280

申请日：2015-09-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Hsien Hsieh ,  Hsien-Wei Chen ,  Chen-Hua Yu ,  Tsung-Shu Lin ,  Wei-Cheng Wu

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/48 ,  H01L23/31

CPC classification number: H01L24/05 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/562 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/35121 ,  H01L2924/00012

Abstract: A redistribution layer with a landing pad is formed over a substrate with one or more mesh holes extending through the landing pad. The mesh holes may be arranged in a circular shape, and a passivation layer may be formed over the landing pad and the mesh holes. An opening is formed through the passivation layer and an underbump metallization is formed in contact with an exposed portion of the landing pad and extends over the mesh holes. By utilizing the mesh holes, sidewall delamination and peeling that might otherwise occur may be reduced or eliminated.

公开(公告)号：US09852957B2

公开(公告)日：2017-12-26

申请号：US15167256

申请日：2016-05-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Hsien Huang ,  Yung-Shou Cheng ,  Yan-Fu Lin ,  An-Jhih Su ,  Wei-Cheng Wu ,  Chin-Hsien Chen ,  Hsien-Wei Chen ,  Der-Chyang Yeh

IPC: H01L21/00 ,  H01L21/66 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L22/14 ,  H01L21/4846 ,  H01L21/76802 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/78 ,  H01L22/20 ,  H01L22/32 ,  H01L23/5389 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2224/83

Abstract: Methods of testing, manufacturing, and packaging semiconductor devices are disclosed. In some embodiments, a method of testing a semiconductor device includes providing an integrated circuit die having contacts disposed thereon, forming an insulating material over the integrated circuit die and the contacts, and forming an opening in the insulating material over the contacts. A eutectic material is formed in the openings over the contacts, and the integrated circuit die is electrically tested by contacting the eutectic material disposed over the contacts. The eutectic material is removed.

公开(公告)号：US20170345726A1

公开(公告)日：2017-11-30

申请号：US15167256

申请日：2016-05-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Hsien Huang ,  Yung-Shou Cheng ,  Yan-Fu Lin ,  An-Jhih Su ,  Wei-Cheng Wu ,  Chin-Hsien Chen ,  Hsien-Wei Chen ,  Der-Chyang Yeh

IPC: H01L21/66 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L22/14 ,  H01L21/4846 ,  H01L21/76802 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/78 ,  H01L22/20 ,  H01L22/32 ,  H01L23/5389 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2224/83

Abstract: Methods of testing, manufacturing, and packaging semiconductor devices are disclosed. In some embodiments, a method of testing a semiconductor device includes providing an integrated circuit die having contacts disposed thereon, forming an insulating material over the integrated circuit die and the contacts, and forming an opening in the insulating material over the contacts. A eutectic material is formed in the openings over the contacts, and the integrated circuit die is electrically tested by contacting the eutectic material disposed over the contacts. The eutectic material is removed.

公开(公告)号：US20170229401A1

公开(公告)日：2017-08-10

申请号：US15494947

申请日：2017-04-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sao-Ling Chiu ,  Kuo-Ching Hsu ,  Wei-Cheng Wu ,  Ping-Kang Huang ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/78 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L24/16 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: A package structure includes an interposer, a die over and bonded to the interposer, and a Printed Circuit Board (PCB) underlying and bonded to the interposer. The interposer is free from transistors therein (add transistor), and includes a semiconductor substrate, an interconnect structure over the semiconductor substrate, through-vias in the silicon substrate, and redistribution lines on a backside of the silicon substrate. The interconnect structure and the redistribution lines are electrically coupled through the through-vias.

公开(公告)号：US20170188458A1

公开(公告)日：2017-06-29

申请号：US14979954

申请日：2015-12-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Hsien Hsieh ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Li-Han Hsu ,  Wei-Cheng Wu

IPC: H05K1/11 ,  H05K1/18

CPC classification number: H05K1/115 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0271 ,  H05K1/111 ,  H05K1/113 ,  H05K1/181 ,  H05K2201/0183 ,  H05K2201/068 ,  H05K2201/09136 ,  H05K2201/09381 ,  H05K2201/0969 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.

公开(公告)号：US20170092604A1

公开(公告)日：2017-03-30

申请号：US14865280

申请日：2015-09-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Hsien Hsieh ,  Hsien-Wei Chen ,  Chen-Hua Yu ,  Tsung-Shu Lin ,  Wei-Cheng Wu

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/48

CPC classification number: H01L24/05 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/562 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/35121 ,  H01L2924/00012

Abstract: A redistribution layer with a landing pad is formed over a substrate with one or more mesh holes extending through the landing pad. The mesh holes may be arranged in a circular shape, and a passivation layer may be formed over the landing pad and the mesh holes. An opening is formed through the passivation layer and an underbump metallization is formed in contact with an exposed portion of the landing pad and extends over the mesh holes. By utilizing the mesh holes, sidewall delamination and peeling that might otherwise occur may be reduced or eliminated.

公开(公告)号：US09570324B2

公开(公告)日：2017-02-14

申请号：US14705555

申请日：2015-05-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Cheng Wu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L21/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/565 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/11 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05573 ,  H01L2224/11002 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/381 ,  H01L2924/00 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684

Abstract: A method of manufacturing a package system includes forming a first interconnect structure over a first surface of a first substrate, forming at least one first through silicon via (TSV) structure in the first substrate, disposing the first substrate over a carrier with the first surface facing the carrier, depositing a molding compound material over the carrier and around the first substrate, forming a second interconnect structure over a second surface of the first substrate, removing the carrier to expose the first interconnect structure over the first surface of the first substrate, and disposing a first integrated circuit over the first surface of the first substrate. The first integrated circuit is electrically coupled with the at least one first TSV structure through the first interconnect structure and connecting bumps.

Abstract translation: 制造封装系统的方法包括在第一衬底的第一表面上形成第一互连结构，在第一衬底中形成至少一个第一穿透硅通孔（TSV）结构，将第一衬底设置在载体上，第一表面 面向载体，在载体上并围绕第一基底沉积模塑复合材料，在第一基底的第二表面上形成第二互连结构，去除载体以在第一基底的第一表面上露出第一互连结构， 以及在所述第一基板的所述第一表面上设置第一集成电路。 第一集成电路通过第一互连结构和连接凸块与至少一个第一TSV结构电耦合。