Invention Application
- Patent Title: Testing, Manufacturing, and Packaging Methods for Semiconductor Devices
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Application No.: US15167256Application Date: 2016-05-27
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Publication No.: US20170345726A1Publication Date: 2017-11-30
- Inventor: Li-Hsien Huang , Yung-Shou Cheng , Yan-Fu Lin , An-Jhih Su , Wei-Cheng Wu , Chin-Hsien Chen , Hsien-Wei Chen , Der-Chyang Yeh
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Main IPC: H01L21/66
- IPC: H01L21/66 ; H01L21/768 ; H01L21/78

Abstract:
Methods of testing, manufacturing, and packaging semiconductor devices are disclosed. In some embodiments, a method of testing a semiconductor device includes providing an integrated circuit die having contacts disposed thereon, forming an insulating material over the integrated circuit die and the contacts, and forming an opening in the insulating material over the contacts. A eutectic material is formed in the openings over the contacts, and the integrated circuit die is electrically tested by contacting the eutectic material disposed over the contacts. The eutectic material is removed.
Public/Granted literature
- US09852957B2 Testing, manufacturing, and packaging methods for semiconductor devices Public/Granted day:2017-12-26
Information query
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