公开(公告)号：US20190122891A1

公开(公告)日：2019-04-25

申请号：US15898420

申请日：2018-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Borna J. Obradovic

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/28158 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/088 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: A method provides a gate structure for a plurality of components of a semiconductor device. A silicate layer is provided. In one aspect, the silicate layer is provided on a channel of a CMOS device. A high dielectric constant layer is provided on the silicate layer. The method also includes providing a work function metal layer on the high dielectric constant layer. A low temperature anneal is performed after the high dielectric constant layer is provided. A contact metal layer is provided on the work function metal layer.

公开(公告)号：US20170098661A1

公开(公告)日：2017-04-06

申请号：US15210867

申请日：2016-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Borna J. Obradovic ,  Rwik Sengupta ,  Wei-E Wang ,  Ryan Hatcher ,  Mark S. Rodder

IPC: H01L27/12 ,  H01L23/528 ,  H01L29/24 ,  H01L29/10 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/84 ,  H01L23/522 ,  H01L29/45

CPC classification number: H01L27/12 ,  H01L21/84 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/528 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/78681

Abstract: A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include one or more transition metal dichalcogenide materials such as MoS2, WS2, WSe2, and/or combinations thereof.

公开(公告)号：US11605574B2

公开(公告)日：2023-03-14

申请号：US17189777

申请日：2021-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Vassilios Gerousis

IPC: H01L23/367 ,  H01L23/373 ,  H01L27/06 ,  H01L25/065 ,  H01L23/522

Abstract: A monolithic three-dimensional integrated circuit including a first device, a second device on the first device, and a thermal shield stack between the first device and the second device. The thermal shield stack includes a thermal retarder portion having a low thermal conductivity in a vertical direction, and a thermal spreader portion having a high thermal conductivity in a horizontal direction. The thermal shield stack of the monolithic three-dimensional integrated circuit includes only dielectric materials.

公开(公告)号：US20210183729A1

公开(公告)日：2021-06-17

申请号：US17189777

申请日：2021-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Vassilios Gerousis

IPC: H01L23/367 ,  H01L23/373 ,  H01L27/06 ,  H01L25/065 ,  H01L23/522

Abstract: A monolithic three-dimensional integrated circuit including a first device, a second device on the first device, and a thermal shield stack between the first device and the second device. The thermal shield stack includes a thermal retarder portion having a low thermal conductivity in a vertical direction, and a thermal spreader portion having a high thermal conductivity in a horizontal direction. The thermal shield stack of the monolithic three-dimensional integrated circuit includes only dielectric materials.

公开(公告)号：US10727297B2

公开(公告)日：2020-07-28

申请号：US15348916

申请日：2016-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Joon Goo Hong

IPC: H01L27/092 ,  H01L29/04 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/78

Abstract: A complimentary metal-oxide-semiconductor (CMOS) circuit including: a substrate; and a plurality of field-effect transistors on the substrate. Each of the field-effect transistors includes: a plurality of contacts; a source connected to one of the contacts; a drain connected to another one of the contacts; a gate; and a spacer between the gate and the contacts. The spacer of one of the field-effect transistors has a larger airgap than the spacer of another one of the field-effect transistors.

公开(公告)号：US20200035838A1

公开(公告)日：2020-01-30

申请号：US16591458

申请日：2019-10-02

Applicant: Samsung Electronics Co., Ltd. ,  Board of Regents, The University of Texas System

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Robert M. Wallace ,  Xiaoye Qin

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/04

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) includes a substrate having a source region, a drain region, and a channel region between the source region and the drain region, the substrate having an epitaxial III-V material that includes three elements thereon, a source electrode over the source region, a drain electrode over the drain region, and a crystalline oxide layer including an oxide formed on the epitaxial III-V material in the channel region, the epitaxial III-V material including three elements.

公开(公告)号：US10475930B2

公开(公告)日：2019-11-12

申请号：US15359480

申请日：2016-11-22

Applicant: Samsung Electronics Co., Ltd. ,  Board of Regents, The University of Texas System

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Robert M. Wallace ,  Xiaoye Qin

IPC: H01L29/10 ,  H01L29/12 ,  H01L29/786 ,  H01L21/02 ,  H01L29/04

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) includes a substrate having a source region, a drain region, and a channel region between the source region and the drain region, the substrate having an epitaxial III-V material that includes three elements thereon, a source electrode over the source region, a drain electrode over the drain region, and a crystalline oxide layer including an oxide formed on the epitaxial III-V material in the channel region, the epitaxial III-V material including three elements.

公开(公告)号：US10026751B2

公开(公告)日：2018-07-17

申请号：US15210867

申请日：2016-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Borna J. Obradovic ,  Rwik Sengupta ,  Wei-E Wang ,  Ryan Hatcher ,  Mark S. Rodder

IPC: H01L27/01 ,  H01L27/12 ,  H01L23/522 ,  H01L23/528 ,  H01L29/24 ,  H01L29/45 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/84 ,  H01L29/10

Abstract: A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include one or more transition metal dichalcogenide materials such as MoS2, WS2, WSe2, and/or combinations thereof.

公开(公告)号：US20180130785A1

公开(公告)日：2018-05-10

申请号：US15442592

申请日：2017-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Titash Rakshit ,  Borna J. Obradovic ,  Chris Bowen ,  Mark S. Rodder

IPC: H01L27/02 ,  H01L23/528 ,  H01L29/04 ,  H01L29/16 ,  H01L23/532 ,  H01L29/47 ,  H01L23/522 ,  H01L21/02 ,  H01L21/28 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/311 ,  H01L27/12 ,  H01L27/092 ,  H01L29/66 ,  H01L27/06

CPC classification number: H01L27/0207 ,  H01L21/02068 ,  H01L21/02164 ,  H01L21/02175 ,  H01L21/02236 ,  H01L21/02244 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/84 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/04 ,  H01L29/16 ,  H01L29/47 ,  H01L29/665

Abstract: A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include polycrystalline silicon. The upper metal routing layer M3 or higher may include cobalt.

公开(公告)号：US09941405B2

公开(公告)日：2018-04-10

申请号：US15340951

申请日：2016-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Wei-E Wang ,  Mark S. Rodder

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/161 ,  H01L21/306 ,  H01L21/3205 ,  H01L29/06 ,  H01L29/417 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/16 ,  H01L29/45 ,  H01L29/165 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L21/30604 ,  H01L21/32055 ,  H01L21/32133 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/456 ,  H01L29/66439 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618

Abstract: A method of manufacturing a nanosheet or nanowire device from a stack including an alternating arrangement of sacrificial layers and channel layers on a substrate. The method includes deep etching portions of the stack to form electrode recesses for a source electrode and a drain electrode, forming conductive passivation layers in the electrode recesses, and epitaxially growing the source and drain electrodes in the electrode recesses. Each conductive passivation layer extends at least partially along a side of one of the electrode recesses. Portions of the substrate at lower ends of the electrode recesses are uncovered by the conductive passivation layers. The source and drain electrodes are grown from the substrate and the conductive passivation layers substantially inhibit the source and drain electrodes from being grown from the channel layers.