公开(公告)号：US10121852B2

公开(公告)日：2018-11-06

申请号：US15794616

申请日：2017-10-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie ,  Derrick Liu ,  Soon-Cheon Seo ,  Stuart A. Sieg

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

公开(公告)号：US10121785B2

公开(公告)日：2018-11-06

申请号：US15397123

申请日：2017-01-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sivananda K. Kanakasabapathy ,  Fee Li Lie ,  Eric Miller ,  Stuart A. Sieg

IPC: H01L21/00 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/308 ,  H01L29/66 ,  H01L21/311 ,  H01L29/16 ,  H01L29/161 ,  H01L29/201 ,  H01L27/092

Abstract: Provided herein is a multi-channel finFET having a plurality of fins prepared by a process. The process includes forming a series of mandrels on hard mask layer which overlays a semiconductor layer. The semiconductor layer has areas of a first semiconductor material and a second semiconductor material in contact with the hard mask layer. The process includes applying a first conformal coating on the hard mask layer and the series of mandrels, to form spacer layer sacrificial fins. The process includes removing the first conformal coating from horizontal surfaces while retaining the first conformal coating on sidewalls of the series of mandrels. The process includes removing the series of mandrels and etching into a material of the hard mask layer using the spacer layer sacrificial fins as a mask.

公开(公告)号：US20180108754A1

公开(公告)日：2018-04-19

申请号：US15297418

申请日：2016-10-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent A. Anderson ,  Bassem M. Hamieh ,  Stuart A. Sieg ,  Junli Wang

IPC: H01L29/66 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L29/786

CPC classification number: H01L29/66553 ,  H01L29/66666 ,  H01L29/78642 ,  H01L29/78696

Abstract: A method includes forming a plurality of fins on a substrate. The method further includes forming a plurality of deep trenches in the substrate and interposed between each fin of the plurality of fins. The method further includes forming a doped semiconductor layer having a uniform thickness, wherein the doped semiconductor layer is formed prior to removing any fins of the plurality of fins.

公开(公告)号：US09882048B2

公开(公告)日：2018-01-30

申请号：US15197996

申请日：2016-06-30

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Sivananda K. Kanakasabapathy ,  Jeffrey C. Shearer ,  Stuart A. Sieg ,  John R. Sporre ,  Junli Wang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/02 ,  H01L29/49

CPC classification number: H01L29/7827 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of cutting a gate on a VFET includes depositing a memorization layer around a spacer on a sidewall of the field effect transistor. A planarizing layer is patterned onto the memorization layer. An anti-reflective coating layer is patterned onto the planarizing layer. A photoresist layer is patterned onto the anti-reflective coating layer on ends of fins extending from a substrate. The planarizing layer, the anti-reflective coating layer, and the photoresist form a mask. The anti-reflective coating layer portion is etched from the VFET. The planarizing layer and the photoresist layer are arc etched from the VFET. The spacer is pulled down forming a void between gates on the VFET and exposing a hard mask on the fins. The hard mask is reactive ion etched vertically around the gates to form gates with a defined width mask. The memorization layer is removed from the VFET.

公开(公告)号：US09876074B2

公开(公告)日：2018-01-23

申请号：US14719829

申请日：2015-05-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie ,  Derrick Liu ,  Soon-Cheon Seo ,  Stuart A. Sieg

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

公开(公告)号：US09721848B1

公开(公告)日：2017-08-01

申请号：US15337189

申请日：2016-10-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Huiming Bu ,  Kangguo Cheng ,  Andrew M. Greene ,  Dechao Guo ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Balasubramanian S. Pranatharthiharan ,  Stuart A. Sieg ,  John R. Sporre ,  Gen Tsutsui ,  Rajasekhar Venigalla ,  Huimei Zhou

IPC: H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L21/823878 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device includes a first fin and a second fin arranged on a substrate, a gate stack arranged over a channel region of the first fin, and spacers arranged along sidewalls of the gate stack. A cavity is arranged adjacent to a distal end of the gate stack. The cavity is defined by the substrate, a distal end of the second fin, and the spacers. A dielectric fill material is arranged in the cavity such that the dielectric fill material contacts the substrate, the distal end of the second fin, and the spacers.

公开(公告)号：US20170162685A1

公开(公告)日：2017-06-08

申请号：US14956711

申请日：2015-12-02

Applicant: International Business Machines Corporation

Inventor： Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Juntao Li ,  Fee Li Lie ,  Stuart A. Sieg ,  John R. Sporre

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/308 ,  H01L29/06

CPC classification number: H01L29/6681 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/42356 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/785

Abstract: Embodiments of the present invention provide a structure and method of minimizing stress relaxation during fin formation. Embodiments may involve forming a looped spacer on an upper surface of a substrate and adjacent to at least a sidewall of a mandrel. The mandrel may be removed, leaving the looped spacer on the substrate. An exposed portion of the substrate may be removed to form a looped fin below the looped spacer. The spacer may be removed, leaving a looped fin. A looped fin formation may reduce stress relaxation compared to conventional fin formation methods. Embodiments may include forming a gate over a looped portion of a looped fin. Securing a looped portion in position with a gate may decrease stress relaxation in the fin. Thus, a looped fin with a looped portion of the looped fin under a gate may have substantially reduced stress relaxation compared to a conventional fin.

公开(公告)号：US09472506B2

公开(公告)日：2016-10-18

申请号：US14630715

申请日：2015-02-25

Applicant: International Business Machines Corporation

Inventor： David J. Conklin ,  Allen H. Gabor ,  Sivananda K. Kanakasabapathy ,  Byeong Y. Kim ,  Fee Li Lie ,  Stuart A. Sieg

IPC: H01L21/308 ,  H01L23/544 ,  H01L21/311 ,  H01L21/033

CPC classification number: H01L23/544 ,  G03F7/70633 ,  G03F7/70683 ,  G03F9/708 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected of the plurality of mandrels and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern of the sub-lithographic structure and the at least one selected mandrel and adjacent spacer for the registration mark. A second etching forms the sub-lithographic structures in the semiconductor layer using the patterned hard mask and to form the registration mark in the semiconductor layer using the at least one selected mandrel and the patterned hard mask.

Abstract translation: 提供了在形成亚光刻结构期间形成诸如对准标记或重叠标记的对准标记的方法。 方法可以包括在半导体层上的硬掩模上形成多个心轴，每个心轴包括与其相邻的间隔物。 选择多个心轴中的至少一个心轴，并且在所述至少一个选定心轴上形成掩模。 离开间隔物去除多个心轴，掩模防止去除至少一个选定的心轴。 去除面具。 第一蚀刻使用间隔物作为亚光刻结构的图案和至少一个选定的心轴和用于对准标记的相邻间隔物，将亚光刻结构和对准标记图案化成硬掩模。 第二蚀刻使用图案化的硬掩模在半导体层中形成次光刻结构，并使用至少一个选定的心轴和图案化的硬掩模在半导体层中形成对准标记。

公开(公告)号：US11121024B2

公开(公告)日：2021-09-14

申请号：US16542502

申请日：2019-08-16

Applicant: International Business Machines Corporation

Inventor： Ekmini A. De Silva ,  Nelson Felix ,  Indira Seshadri ,  Stuart A. Sieg

IPC: H01L21/762 ,  H01L23/544 ,  H01L21/027 ,  H01L21/768 ,  H01L21/48 ,  B82Y40/00

Abstract: A tunable amorphous silicon layer for use with multilayer patterning stacks can be used to maximize transparency and minimize reflections so as to improve overlay metrology contrast. By increasing the hydrogen content in the amorphous silicon layer, the extinction coefficient (k) value and the refractive index (n) value can be decreased to desired values. Methods for improving overlay metrology contrast with the tunable amorphous silicon layer are disclosed.

公开(公告)号：US10734372B2

公开(公告)日：2020-08-04

申请号：US15923683

申请日：2018-03-16

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Stuart A. Sieg ,  Junli Wang

IPC: H01L27/02 ,  H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/786 ,  H01L21/02 ,  G11C11/41 ,  G11C11/412

Abstract: A semiconductor structure includes a vertical transport static random-access memory (SRAM) cell having a first active region and a second active region. The first active region and the second active region are linearly arranged in first and second rows, respectively. The first row of the first active region includes a first pull-up transistor, a first pull-down transistor and a first pass gate transistor, and the second row of the second active region includes a second pull-up transistor, a second pull-down transistor and a second pass gate transistor. A first gate region of the first active region extends orthogonal from the first row to the second active region, and a second gate region of the second active region extends orthogonal from the second row to the first active region.