公开(公告)号：US10943911B2

公开(公告)日：2021-03-09

申请号：US15955283

申请日：2018-04-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent A. Anderson ,  Stuart A. Sieg ,  Junli Wang

IPC: H01L27/11 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/762

Abstract: In accordance with an embodiment of the present invention, a memory cell is provided. The memory cell includes a first L-shaped bottom source/drain including a first dopant, and a first adjoining bottom source/drain region abutting the first L-shaped bottom source/drain, wherein the first adjoining bottom source/drain region includes a second dopant that is the opposite type from the first dopant.

公开(公告)号：US10741452B2

公开(公告)日：2020-08-11

申请号：US16173378

申请日：2018-10-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Eric R. Miller ,  Stuart A. Sieg ,  Yann Mignot ,  Indira Seshadri ,  Christopher J. Waskiewicz

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/033 ,  H01L29/66 ,  H01L27/088

Abstract: Methods for forming semiconductor fins include forming a sacrificial semiconductor structure around a hardmask fin on an underlying semiconductor layer. A first etch is performed that partially etches away a portion of the hardmask fin and the sacrificial semiconductor structure with a first etch chemistry. A second etch is performed that etches away remaining material of the portion of the hardmask fin and partially etches remaining material of the sacrificial semiconductor structure with a second etch chemistry. A semiconductor fin is etched from the semiconductor layer using the etched hardmask fin as a mask.

公开(公告)号：US20200075761A1

公开(公告)日：2020-03-05

申请号：US16114613

申请日：2018-08-28

Applicant: International Business Machines Corporation

Inventor： Praveen Joseph ,  Indira Seshadri ,  Ekmini A. De Silva ,  Stuart A. Sieg

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/033 ,  H01L21/02 ,  H01L29/08

Abstract: A semiconductor device includes a semiconductor fin that extends from a first source/drain to an opposing second source/drain. The semiconductor fin includes a channel region between the first and second source/drains. The semiconductor device further includes a spacer having an upper surface having the second source/drain formed thereon, and a gate structure a gate structure wrapping around the channel region. The gate structure includes a tapered portion that contacts the spacer.

公开(公告)号：US20190319032A1

公开(公告)日：2019-10-17

申请号：US15955283

申请日：2018-04-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent A. Anderson ,  Stuart A. Sieg ,  Junli Wang

IPC: H01L27/11 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L21/762 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/06

Abstract: In accordance with an embodiment of the present invention, a memory cell is provided. The memory cell includes a first L-shaped bottom source/drain including a first dopant, and a first adjoining bottom source/drain region abutting the first L-shaped bottom source/drain, wherein the first adjoining bottom source/drain region includes a second dopant that is the opposite type from the first dopant.

公开(公告)号：US20190206722A1

公开(公告)日：2019-07-04

申请号：US15861774

申请日：2018-01-04

Applicant: International Business Machines Corporation

Inventor： Ekmini A. De Silva ,  Nelson Felix ,  Indira Seshadri ,  Stuart A. Sieg

IPC: H01L21/762 ,  H01L23/544 ,  H01L21/027 ,  H01L21/48 ,  H01L21/768

CPC classification number: H01L21/76294 ,  B82Y40/00 ,  H01L21/0272 ,  H01L21/4885 ,  H01L21/768 ,  H01L23/544 ,  H01L2223/54426

Abstract: A tunable amorphous silicon layer for use with multilayer patterning stacks can be used to maximize transparency and minimize reflections so as to improve overlay metrology contrast. By increasing the hydrogen content in the amorphous silicon layer, the extinction coefficient (k) value and the refractive index (n) value can be decreased to desired values. Methods for improving overlay metrology contrast with the tunable amorphous silicon layer are disclosed.

公开(公告)号：US10312103B2

公开(公告)日：2019-06-04

申请号：US15445112

申请日：2017-02-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sean D. Burns ,  Nelson M. Felix ,  Chi-Chun Liu ,  Yann A. M. Mignot ,  Stuart A. Sieg

IPC: H01L21/308 ,  H01L21/3065 ,  H01L29/66

Abstract: A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern has hardmask fins of three mutually selectively etchable compositions. A region on the three-color hardmask fin pattern is masked, leaving one or more fins of a first color exposed. All exposed fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color. The mask and all fins of a second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.

公开(公告)号：US10242952B2

公开(公告)日：2019-03-26

申请号：US16041878

申请日：2018-07-23

Applicant: International Business Machines Corporation

Inventor： David J. Conklin ,  Allen H. Gabor ,  Sivananda K. Kanakasabapathy ,  Byeong Y. Kim ,  Fee Li Lie ,  Stuart A. Sieg

IPC: H01L21/311 ,  H01L23/544 ,  H01L21/308 ,  G03F7/20 ,  H01L21/033 ,  G03F9/00

Abstract: Methods of forming a registration mark may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern and the at least one selected mandrel and adjacent spacer for the registration mark. A second etching forms the sub-lithographic structures in the semiconductor layer using the patterned hard mask and to form the registration mark in the semiconductor layer using the at least one selected mandrel and the patterned hard mask.

公开(公告)号：US10211319B2

公开(公告)日：2019-02-19

申请号：US15633934

申请日：2017-06-27

Applicant: International Business Machines Corporation

Inventor： Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Juntao Li ,  Fee Li Lie ,  Stuart A. Sieg ,  John R. Sporre

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/308 ,  H01L29/423 ,  H01L21/84 ,  H01L27/12

Abstract: Embodiments of the present invention provide a structure and method of minimizing stress relaxation during fin formation. Embodiments may involve forming a looped spacer on an upper surface of a substrate and adjacent to at least a sidewall of a mandrel. The mandrel may be removed, leaving the looped spacer on the substrate. An exposed portion of the substrate may be removed to form a looped fin below the looped spacer. The spacer may be removed, leaving a looped fin. A looped fin formation may reduce stress relaxation compared to conventional fin formation methods. Embodiments may include forming a gate over a looped portion of a looped fin. Securing a looped portion in position with a gate may decrease stress relaxation in the fin. Thus, a looped fin with a looped portion of the looped fin under a gate may have substantially reduced stress relaxation compared to a conventional fin.

公开(公告)号：US10043760B2

公开(公告)日：2018-08-07

申请号：US15794637

申请日：2017-10-26

Applicant: International Business Machines Corporation

Inventor： David J. Conklin ,  Allen H. Gabor ,  Sivananda K. Kanakasabapathy ,  Byeong Y. Kim ,  Fee Li Lie ,  Stuart A. Sieg

IPC: H01L21/311 ,  H01L23/544 ,  H01L21/308 ,  G03F9/00 ,  G03F7/20 ,  H01L21/033

CPC classification number: H01L23/544 ,  G03F7/70633 ,  G03F7/70683 ,  G03F9/708 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected of the plurality of mandrels and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern of the sub-lithographic structure and the at least one selected mandrel and adjacent spacer for the registration mark. A second etching forms the sub-lithographic structures in the semiconductor layer using the patterned hard mask and to form the registration mark in the semiconductor layer using the at least one selected mandrel and the patterned hard mask.

公开(公告)号：US20150311121A1

公开(公告)日：2015-10-29

申请号：US14260724

申请日：2014-04-24

Applicant: International Business Machines Corporation

Inventor： Kevin S. Petrarca ,  Stuart A. Sieg ,  Theodorus E. Standaert

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/308 ,  H01L21/311 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L21/823431 ,  H01L21/02123 ,  H01L21/0337 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A trench isolation structure is formed beneath a topmost surface of a semiconductor substrate. A mandrel structure having a bottommost surface that straddles a sidewall edge of the underlying trench isolation structure is then formed. Nitride spacers are formed on sidewalls of the mandrel structure and thereafter the mandrel structure is removed. A dielectric oxide material is then formed having a topmost surface that is coplanar with a topmost surface of each remaining nitride spacer. Each nitride spacer is removed and thereafter a semiconductor fin is epitaxially grown within a cavity in the dielectric oxide material which exposes a topmost surface of the semiconductor substrate.

Abstract translation: 沟槽隔离结构形成在半导体衬底的最上表面之下。 然后形成具有跨越下面的沟槽隔离结构的侧壁边缘的最底表面的心轴结构。 氮化物间隔件形成在心轴结构的侧壁上，然后去除心轴结构。 然后形成电介质氧化物材料，其具有与每个剩余的氮化物间隔物的最上表面共面的最顶表面。 去除每个氮化物间隔物，然后在暴露半导体衬底的最上表面的电介质氧化物材料的腔内外延生长半导体鳍。