公开(公告)号：US10580652B2

公开(公告)日：2020-03-03

申请号：US16058088

申请日：2018-08-08

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： John C. Arnold ,  Anuja E. DeSilva ,  Nelson M. Felix ,  Chi-Chun Liu ,  Yann A. M. Mignot ,  Stuart A. Sieg

IPC分类号： H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/8234

摘要： Methods of forming fins include masking a region on a three-color hardmask fin pattern, leaving a fin of a first color exposed. The exposed fin of the first color is etched away with a selective etch that does not remove fins of a second color or a third color. The mask and all fins of a second color are etched away. Fins are etched into a fin base layer using the fins of the first color and the fins of the third color.

公开(公告)号：US10062605B2

公开(公告)日：2018-08-28

申请号：US15589229

申请日：2017-05-08

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Yann A. M. Mignot ,  Theodorus E. Standaert ,  Chih-Chao Yang

IPC分类号： H01L21/768 ,  H01L21/311

CPC分类号： H01L21/76844 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32131 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76865

摘要： Methods of forming a semiconductor structure includes etching a via opening through an interlevel dielectric to a metal conductor. A contiguous metal liner is deposited onto exposed surfaces of the substrate. The substrate is exposed to a gaseous ion plasma to remove portions of the metal liner that are horizontally oriented and to reduce a height of the metal liner from portions thereof that are vertically oriented. Subsequently, a trench opening is formed in the interlevel dielectric, wherein the trench opening is connected with the via opening, wherein at least a portion of the metal liner remains on sidewall surfaces within the via opening during the forming of the trench opening. A diffusion barrier liner is deposited within the trench opening and the via opening. A conductive material is formed within remaining portions of the trench opening and the via opening to define the interconnect structure.

公开(公告)号：US10043744B2

公开(公告)日：2018-08-07

申请号：US15800154

申请日：2017-11-01

申请人： International Business Machines Corporation

发明人： Victor W. C. Chan ,  Xuefeng Liu ,  Yann A. M. Mignot ,  Yongan Xu

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768

摘要： Techniques relate to forming a gate metal via. A gate contact has a bottom part in a first layer. A cap layer is formed on the gate contact and first layer. The gate contact is formed on top of the gate. A second layer is formed on the cap layer. The second layer and cap layer are recessed to remove a portion of the cap layer from a top part and upper sidewall parts of the gate contact. A third layer is formed on the second layer, cap layer, and gate contact. The third layer is etched through to form a gate trench over the gate contact to be around the upper sidewall parts of the gate contact. The gate trench is an opening that stops on the cap layer. Gate metal via is formed on top of the gate contact and around upper sidewall parts of the gate contact.

公开(公告)号：US09786554B1

公开(公告)日：2017-10-10

申请号：US15176284

申请日：2016-06-08

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Sean D. Burns ,  Lawrence A. Clevenger ,  Anuja E. DeSilva ,  Nelson M. Felix ,  Sivananda K. Kanakasabapathy ,  Yann A. M. Mignot ,  Christopher J. Penny ,  Roger A. Quon ,  Nicole A. Saulnier

IPC分类号： H01L21/768 ,  H01L23/528

CPC分类号： H01L21/76877 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76897 ,  H01L23/528

摘要： A method for forming conductive lines on a wafer comprises forming a first hardmask, a planarizing layer, a second hardmask, a layer of sacrificial mandrel material on the second hardmask, and patterning a mask on the layer of sacrificial material. A first sacrificial mandrel and a second sacrificial mandrel and a gap are formed. A layer of spacer material is deposited in the gap. Portions of the first sacrificial mandrel and the second sacrificial mandrel are removed, and exposed portions of the second hardmask, the planarizing layer and the first hardmask are removed to expose portions of the insulator layer. The second hardmask, the spacers, and the planarizing layer are removed. Exposed portions of the insulator layer are removed to form a trench in the insulator layer, and the trench is filled with a conductive material.

公开(公告)号：US10090378B1

公开(公告)日：2018-10-02

申请号：US15462501

申请日：2017-03-17

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kisup Chung ,  Isabel C. Estrada-Raygoza ,  Hemanth Jagannathan ,  Chi-Chun Liu ,  Yann A. M. Mignot ,  Hao Tang

IPC分类号： H01L49/02

摘要： Capacitors and methods of forming the same include forming a self-assembled pattern of periodic first and second domains using first and second block copolymer materials over a substrate. The second block copolymer material is etched away. Material from the substrate is etched based on a pattern defined by the first block copolymer material to form cavities in the substrate. A capacitor stack is conformally deposited over the substrate, such that the capacitor stack is formed on horizontal surfaces of the substrate and vertical surfaces of the cavities.

公开(公告)号：US10090164B2

公开(公告)日：2018-10-02

申请号：US15404465

申请日：2017-01-12

申请人： International Business Machines Corporation

发明人： Ekmini A. De Silva ,  Isabel C. Estrada-Raygoza ,  Yann A. M. Mignot ,  Indira P. V. Seshadri ,  Yongan Xu

IPC分类号： H01L21/027 ,  H01L21/308 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/3105 ,  H01L29/06

摘要： Embodiments are directed to a method of forming a semiconductor device and resulting structures having a hard masks for sidewall image transfer (SIT) block patterning. The method includes forming a first hard mask on a substrate. Spacers are formed on the first hard mask, and a second hard mask is formed over the spacers. The second hard mask and a portion of the first hard mask are concurrently removed by the same hard mask removal process to expose a surface of the substrate. After concurrently removing the second hard mask and portions of the first hard mask, the heights of the spacers are substantially equal.

公开(公告)号：US20180197745A1

公开(公告)日：2018-07-12

申请号：US15897390

申请日：2018-02-15

申请人： International Business Machines Corporation

发明人： Ekmini A. De Silva ,  Isabel C. Estrada-Raygoza ,  Yann A. M. Mignot ,  Indira P. V. Seshadri ,  Yongan Xu

IPC分类号： H01L21/308 ,  H01L29/06 ,  H01L21/3105

CPC分类号： H01L21/3081 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31051 ,  H01L29/0657

摘要： Embodiments are directed to a method of forming a semiconductor device and resulting structures having a hard masks for sidewall image transfer (SIT) block patterning. The method includes forming a first hard mask on a substrate. Spacers are formed on the first hard mask, and a second hard mask is formed over the spacers. The second hard mask and a portion of the first hard mask are concurrently removed by the same hard mask removal process to expose a surface of the substrate. After concurrently removing the second hard mask and portions of the first hard mask, the heights of the spacers are substantially equal.

公开(公告)号：US20180197744A1

公开(公告)日：2018-07-12

申请号：US15404465

申请日：2017-01-12

申请人： International Business Machines Corporation

发明人： Ekmini A. De Silva ,  Isabel C. Estrada-Raygoza ,  Yann A. M. Mignot ,  Indira P. V. Seshadri ,  Yongan Xu

IPC分类号： H01L21/308 ,  H01L21/3105 ,  H01L29/06

CPC分类号： H01L21/3081 ,  H01L21/3086 ,  H01L21/31051 ,  H01L29/0657

摘要： Embodiments are directed to a method of forming a semiconductor device and resulting structures having a hard masks for sidewall image transfer (SIT) block patterning. The method includes forming a first hard mask on a substrate. Spacers are formed on the first hard mask, and a second hard mask is formed over the spacers. The second hard mask and a portion of the first hard mask are concurrently removed by the same hard mask removal process to expose a surface of the substrate. After concurrently removing the second hard mask and portions of the first hard mask, the heights of the spacers are substantially equal.

公开(公告)号：US09991156B2

公开(公告)日：2018-06-05

申请号：US15172265

申请日：2016-06-03

申请人： International Business Machines Corporation

发明人： Sean D. Burns ,  Lawrence A. Clevenger ,  Matthew E. Colburn ,  Sivananda K. Kanakasabapathy ,  Yann A. M. Mignot ,  Christopher J. Penny ,  Roger A. Quon ,  Nicole A. Saulnier

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76816 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02697 ,  H01L21/027 ,  H01L21/0338 ,  H01L21/31116 ,  H01L21/76885 ,  H01L21/76886 ,  H01L21/76892 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53266

摘要： An interconnect structure having a pitch of less than 40 nanometers and a self-aligned quadruple patterning process for forming the interconnect structure includes three types of lines: a β line defined by a patterned bottom mandrel formed in the self-aligned quadruple patterning process; a γ line defined by location underneath a top mandrel formed in the self-aligned quadruple patterning process; and an α line defined by elimination located underneath neither the top mandrel or the bottom mandrel formed in the self-aligned quadruple patterning process. The interconnect structure further includes multi-track jogs selected from a group consisting of a βγβ jog; a βαβ jog; an αβγ jog; a γβα jog, and combinations thereof. The first and third positions refer to the uncut line and the second position refers to the cut line in the self-aligned quadruple patterning process.

公开(公告)号：US20170358487A1

公开(公告)日：2017-12-14

申请号：US15677447

申请日：2017-08-15

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Sean D. Burns ,  Lawrence A. Clevenger ,  Anuja E. DeSilva ,  Nelson M. Felix ,  Sivananda K. Kanakasabapathy ,  Yann A. M. Mignot ,  Christopher J. Penny ,  Roger A. Quon ,  Nicole A. Saulnier

IPC分类号： H01L21/768 ,  H01L23/528

CPC分类号： H01L21/76877 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76897 ,  H01L23/528

摘要： A method for forming conductive lines on a wafer comprises forming a first hardmask, a planarizing layer, a second hardmask, a layer of sacrificial mandrel material on the second hardmask, and patterning a mask on the layer of sacrificial material. A first sacrificial mandrel and a second sacrificial mandrel and a gap are formed. A layer of spacer material is deposited in the gap. Portions of the first sacrificial mandrel and the second sacrificial mandrel are removed, and exposed portions of the second hardmask, the planarizing layer and the first hardmask are removed to expose portions of the insulator layer. The second hardmask, the spacers, and the planarizing layer are removed. Exposed portions of the insulator layer are removed to form a trench in the insulator layer, and the trench is filled with a conductive material.