公开(公告)号：US20130260549A1

公开(公告)日：2013-10-03

申请号：US13771937

申请日：2013-02-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hemanth Jagannathan ,  Ramachandra Divakaruni ,  Unoh Kwon ,  Vijay Narayanan ,  Ravikumar Ramachandran

IPC: H01L21/285

CPC classification number: H01L21/28518 ,  H01L21/26506 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/105 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

Abstract: Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material, which provides, in combination with other layer, a work function about 4.4 eV or less, and can include a material selected from tantalum carbide, metallic nitrides, and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel. Optionally, carbon doping can be introduced in the channel.

Abstract translation: 提供了替代栅极工作功能材料堆叠，其提供关于硅导带的能级的功函数。 在去除一次性栅极堆叠之后，在栅极腔中形成栅极电介质层。 包括金属和非金属元素的金属化合物层直接沉积在栅极介电层上。 沉积至少一个势垒层和导电材料层并平坦化以填充栅极腔。 金属化合物层包括与其它层组合提供约4.4eV或更低的功函数的材料，并且可以包括选自碳化钽，金属氮化物和铪硅合金的材料。 因此，金属化合物层可以提供增强采用硅通道的n型场效应晶体管的性能的功函数。 任选地，可以在通道中引入碳掺杂。

公开(公告)号：US11935929B2

公开(公告)日：2024-03-19

申请号：US17507385

申请日：2021-10-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Julien Frougier ,  Su Chen Fan ,  Ravikumar Ramachandran ,  Nicolas Loubet

IPC: H01L29/417 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/40 ,  H01L29/45

CPC classification number: H01L29/41725 ,  H01L21/823871 ,  H01L23/5286 ,  H01L27/0922 ,  H01L29/401 ,  H01L29/45

Abstract: A stacked device is provided. The stacked device includes a reduced height active device layer, and a plurality of lower source/drain regions in the reduced height active device layer. The stacked device further includes a lower interlayer dielectric (ILD) layer on the plurality of lower source/drain regions, and a conductive trench spacer in the lower interlayer dielectric (ILD) layer, wherein the conductive trench spacer is adjacent to one of the plurality of lower source/drain regions. The stacked device further includes a top active device layer adjacent to the lower interlayer dielectric (ILD) layer, and an upper source/drain section in the top active device layer. The stacked device further includes a shared contact in electrical connection with the upper source/drain section, the conductive trench spacer, and the one of the plurality of lower source/drain regions.

公开(公告)号：US20230411358A1

公开(公告)日：2023-12-21

申请号：US17807765

申请日：2022-06-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Albert M. Chu ,  Albert M. Young ,  Brent A. Anderson ,  Junli Wang ,  Ravikumar Ramachandran

IPC: H01L25/07 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L25/071 ,  H01L21/02507 ,  H01L21/8221 ,  H01L29/0673 ,  H01L21/823431 ,  H01L29/66545 ,  H01L21/02603

Abstract: A microelectronic structure including a plurality of lower transistors and a plurality of upper transistor, where each of the plurality of lower transistors and the plurality of upper transistors includes a plurality of channel. Where an upper center vertical axis of each of the plurality of upper transistors is staggered from a lower center vertical axis of each of the lower transistors. A lower gate cut is located between each of the plurality of lower transistors. A first upper gate cut located adjacent to a first upper transistor of the plurality of upper transistors, where the first upper gate cut is in direct contact with a plurality of first channels of the first upper transistor.

公开(公告)号：US10256238B2

公开(公告)日：2019-04-09

申请号：US16038600

申请日：2018-07-18

Applicant: International Business Machines Corporation

Inventor： Andrew M. Greene ,  Dechao Guo ,  Ravikumar Ramachandran ,  Rajasekhar Venigalla

IPC: H01L21/336 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/308 ,  H01L29/66 ,  H01L21/311 ,  H01L29/06 ,  H01L21/306 ,  H01L29/78

Abstract: A method of forming a semiconductor structure includes forming a fin cut mask over a region in a fin field-effect transistor (finFET) structure. The finFET structure includes one or more fins and one or more gates and source/drain regions formed over the one or more fins in active regions of the finFET structure. The method also includes performing a fin cut by removing a portion of at least one fin. The portion of the at least one fin is determined by an exposed area of the fin cut mask. The exposed area of the fin cut mask includes at least a portion of the at least one fin between a first dummy gate and a second dummy gate formed over the at least one fin. The method further includes removing the fin cut mask and depositing an oxide to replace the portion of the at least one fin removed during the fin cut.

公开(公告)号：US10177154B2

公开(公告)日：2019-01-08

申请号：US15691182

申请日：2017-08-30

Applicant: International Business Machines Corporation

Inventor： Michael V. Aquilino ,  Veeraraghavan S. Basker ,  Kangguo Cheng ,  Gregory Costrini ,  Ali Khakifirooz ,  Byeong Y. Kim ,  William L. Nicoll ,  Ravikumar Ramachandran ,  Reinaldo A. Vega ,  Hanfei Wang ,  Xinhui Wang

IPC: H01L29/94 ,  H01L27/108 ,  H01L27/12 ,  H01L27/08

Abstract: After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure having a base portion vertically contacting a deep trench capacitor embedded in a substrate and a fin portion laterally contacting the semiconductor fin, conducting spikes that are formed on the sidewalls of the deep trench are removed or pushed deeper into the deep trench. Subsequently, a dielectric cap that inhibits epitaxial growth of a semiconductor material thereon is formed over at least a portion of the base portion of the conductive strap structure. The dielectric cap can be formed either over an entirety of the base portion having a stepped structure or on a distal portion of the base portion.

公开(公告)号：US20180323193A1

公开(公告)日：2018-11-08

申请号：US16038488

申请日：2018-07-18

Applicant: International Business Machines Corporation

Inventor： Andrew M. Greene ,  Dechao Guo ,  Ravikumar Ramachandran ,  Rajasekhar Venigalla

IPC: H01L27/088 ,  H01L21/306 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L21/311 ,  H01L21/308

CPC classification number: H01L27/0886 ,  H01L21/30625 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7851

Abstract: A method of forming a semiconductor structure includes forming a fin cut mask over a region in a fin field-effect transistor (finFET) structure. The finFET structure includes one or more fins and one or more gates and source/drain regions formed over the one or more fins in active regions of the finFET structure. The method also includes performing a fin cut by removing a portion of at least one fin. The portion of the at least one fin is determined by an exposed area of the fin cut mask. The exposed area of the fin cut mask includes at least a portion of the at least one fin between a first dummy gate and a second dummy gate formed over the at least one fin. The method further includes removing the fin cut mask and depositing an oxide to replace the portion of the at least one fin removed during the fin cut.

公开(公告)号：US20170365606A1

公开(公告)日：2017-12-21

申请号：US15691182

申请日：2017-08-30

Applicant: International Business Machines Corporation

Inventor： Michael V. Aquilino ,  Veeraraghavan S. Basker ,  Kangguo Cheng ,  Gregory Costrini ,  Ali Khakifirooz ,  Byeong Y. Kim ,  William L. Nicoll ,  Ravikumar Ramachandran ,  Reinaldo A. Vega ,  Hanfei Wang ,  Xinhui Wang

IPC: H01L27/108 ,  H01L27/12

CPC classification number: H01L27/1087 ,  H01L27/0817 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/10879 ,  H01L27/1203

Abstract: After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure having a base portion vertically contacting a deep trench capacitor embedded in a substrate and a fin portion laterally contacting the semiconductor fin, conducting spikes that are formed on the sidewalls of the deep trench are removed or pushed deeper into the deep trench. Subsequently, a dielectric cap that inhibits epitaxial growth of a semiconductor material thereon is formed over at least a portion of the base portion of the conductive strap structure. The dielectric cap can be formed either over an entirety of the base portion having a stepped structure or on a distal portion of the base portion.

公开(公告)号：US20170040320A1

公开(公告)日：2017-02-09

申请号：US15331351

申请日：2016-10-21

Applicant: International Business Machines Corporation

Inventor： Henry K. Utomo ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Ravikumar Ramachandran ,  Huiling Shang ,  Reinaldo A. Vega

IPC: H01L27/088 ,  H01L29/167 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate. The combination of the second semiconductor material and the dopant within the well trapping layer is selected such that diffusion of the dopant is limited within the well trapping layer. A device semiconductor material layer including a third semiconductor material can be epitaxially grown on the top surface of the well trapping layer. The device semiconductor material layer, the well trapping layer, and an upper portion of the bulk semiconductor substrate are patterned to form at least one semiconductor fin. Semiconductor devices formed in each semiconductor fin can be electrically isolated from the bulk semiconductor substrate by the remaining portions of the well trapping layer.

Abstract translation: 提供了包括第一半导体材料的体半导体衬底。 包括第二半导体材料和掺杂剂的阱捕获层形成在体半导体衬底的顶表面上。 阱阱捕获层内的第二半导体材料和掺杂剂的组合被选择为使得掺杂剂的扩散受限于阱捕获层内。 包括第三半导体材料的器件半导体材料层可以在阱捕获层的顶表面上外延生长。 图案化器件半导体材料层，阱捕获层和体半导体衬底的上部以形成至少一个半导体鳍。 形成在每个半导体鳍片中的半导体器件可以通过阱捕获层的其余部分与体半导体衬底电隔离。

公开(公告)号：US20160336266A1

公开(公告)日：2016-11-17

申请号：US15219413

申请日：2016-07-26

Applicant: International Business Machines Corporation

Inventor： Rosa A. Orozco-Teran ,  Ravikumar Ramachandran ,  John A. Fitzsimmons ,  David L. Rath

IPC: H01L23/528 ,  H01L21/28 ,  H01L29/49 ,  H01L23/532 ,  H01L29/423 ,  H01L29/45 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/28079 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L29/41775 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/4958 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of present invention provide a method of forming a semiconductor structure. The method includes forming a semiconductor structure having a first metal layer and a plurality of dielectric layers on top of the first metal layer; creating one or more openings through the plurality of dielectric layers to expose the first metal layer underneath the plurality of dielectric layers; causing the one or more openings to expand downward into the first metal layer and expand horizontally into areas underneath the plurality of dielectric layers; applying a layer of lining material in lining sidewalls of the one or more openings inside the plurality of dielectric layers; and filling the expanded one or more openings with a conductive material.

Abstract translation: 本发明的实施例提供一种形成半导体结构的方法。 该方法包括在第一金属层的顶部上形成具有第一金属层和多个电介质层的半导体结构; 通过所述多个电介质层产生一个或多个开口以暴露所述多个电介质层下面的所述第一金属层; 使所述一个或多个开口向下扩展到所述第一金属层中并且水平地扩展到所述多个介电层下面的区域中; 在所述多个电介质层内的所述一个或多个开口的衬里侧壁中施加一层衬里材料; 并用导电材料填充膨胀的一个或多个开口。

公开(公告)号：US09368593B2

公开(公告)日：2016-06-14

申请号：US14875049

申请日：2015-10-05

Applicant: International Business Machines Corporation

Inventor： Unoh Kwon ,  Wing L. Lai ,  Vijay Narayanan ,  Sean M. Polvino ,  Ravikumar Ramachandran ,  Shahab Siddiqui

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/51 ,  H01L29/40 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/513 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/401 ,  H01L29/42368 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66545

Abstract: After removal of the disposable gate structures to form gate cavities in a planarization dielectric layer, a silicon oxide layer is conformally deposited on silicon-oxide-based gate dielectric portions in the gate cavities. A portion of the silicon oxide layer can be nitridated to form a silicon oxynitride layer. A patterned masking material layer can be employed to physically expose a semiconductor surface from a first-type gate cavity. The silicon oxide layer can be removed while preserving an underlying silicon-oxide-based gate dielectric portion in a second-type gate cavity. A stack of a silicon oxynitride layer and an underlying silicon-oxide-based gate dielectric can be protected by a patterned masking material layer in a third-type gate cavity during removal of the silicon oxide layer in the second-type gate cavity. A high dielectric constant gate dielectric layer can be formed in the gate cavities to provide gate dielectrics of different types.