公开(公告)号：US11791421B2

公开(公告)日：2023-10-17

申请号：US17574844

申请日：2022-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Bo-Feng Young ,  Chien Ning Yao ,  Chi On Chui

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/78696 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes: a fin protruding above a substrate; source/drain regions over the fin; nanosheets between the source/drain regions, where the nanosheets comprise a first semiconductor material; inner spacers between the nanosheets and at opposite ends of the nanosheets, where there is an air gap between each of the inner spacers and a respective source/drain region of the source/drain regions; and a gate structure over the fin and between the source/drain regions.

公开(公告)号：US20230317790A1

公开(公告)日：2023-10-05

申请号：US18152601

申请日：2023-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Teng Chuang ,  Kuei-Lun Lin ,  Te-Yang Lai ,  Da-Yuan Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/423 ,  H01L21/8234

CPC classification number: H01L29/0673 ,  H01L29/78696 ,  H01L29/42384 ,  H01L21/823412

Abstract: In an embodiment, a semiconductor device is provided, which includes a first doped gate dielectric layer and a second doped gate dielectric layer, wherein the first doped gate dielectric layer and the second doped gate dielectric layer comprise a high-k material doped with a dipole dopant. The second doped gate dielectric layer has a second concentration of the first dipole dopant. The concentration of the dipole dopant in the first doped gate dielectric layer is greater than the concentration, and the concentration peak of the dipole dopant in the first doped gate dielectric layer is deeper than the concentration peak of the dipole dopant in the second doped gate dielectric layer. A first gate electrode over the first doped gate dielectric layer, and a second gate electrode over the second doped gate dielectric layer, the first gate electrode and the second gate electrode have a same width.

公开(公告)号：US20230299177A1

公开(公告)日：2023-09-21

申请号：US18324442

申请日：2023-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Chi On Chui

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/06 ,  C23C18/16 ,  H01L21/8238 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L29/401 ,  H01L29/0665 ,  C23C18/1657 ,  H01L29/66742 ,  H01L21/823871 ,  H01L29/42392

Abstract: Embodiments utilize an electro-chemical process to deposit a metal gate electrode in a gate opening in a gate replacement process for a nanosheet FinFET device. Accelerators and suppressors may be used to achieve a bottom-up deposition for a fill material of the metal gate electrode.

公开(公告)号：US20230268416A1

公开(公告)日：2023-08-24

申请号：US18311035

申请日：2023-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu

IPC: H01L29/49 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L29/4983 ,  H01L21/823871 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/66492 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66795 ,  H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L27/0924

Abstract: Semiconductor devices and methods of manufacture are presented in which spacers are manufactured on sidewalls of gates for semiconductor devices. In embodiments the spacers comprise a first seal, a second seal, and a contact etch stop layer, in which the first seal comprises a first shell along with a first bulk material, the second seal comprises a second shell along with a second bulk material, and the contact etch stop layer comprises a third bulk material and a second dielectric material.

公开(公告)号：US20230261051A1

公开(公告)日：2023-08-17

申请号：US18302132

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L29/0673 ,  H01L29/7851 ,  H01L29/66795 ,  H01L27/0924

Abstract: In an embodiment, a device includes: a channel region; a gate dielectric layer on the channel region; a first work function tuning layer on the gate dielectric layer, the first work function tuning layer including a p-type work function metal; a barrier layer on the first work function tuning layer; a second work function tuning layer on the barrier layer, the second work function tuning layer including a n-type work function metal, the n-type work function metal different from the p-type work function metal; and a fill layer on the second work function tuning layer.

公开(公告)号：US11728173B2

公开(公告)日：2023-08-15

申请号：US17038499

申请日：2020-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ju Chen ,  Chung-Ting Ko ,  Wan-Chen Hsieh ,  Chun-Ming Lung ,  Tai-Chun Huang ,  Chi On Chui

IPC: H01L21/308 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L21/3085 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02356 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.

公开(公告)号：US11721699B2

公开(公告)日：2023-08-08

申请号：US17157182

申请日：2021-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Hung Cheng Lin ,  Chunyao Wang ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a dielectric fin is formed in order to help isolate adjacent semiconductor fins. The dielectric fin is formed using a deposition process in which deposition times and temperatures are utilized to increase the resistance of the dielectric fin to subsequent etching processes.

公开(公告)号：US20230240066A1

公开(公告)日：2023-07-27

申请号：US17747389

申请日：2022-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Bo-Feng Young ,  Chi On Chui

IPC: H01L27/108 ,  G11C5/06 ,  H01L29/423

CPC classification number: H01L27/10841 ,  G11C5/063 ,  H01L27/10814 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/4236

Abstract: Embodiments provide an integrated capacitor disposed directly over and aligned to a vertical gate all around memory cell transistor. In some embodiments, an air gap may be provided between adjacent word lines to provide a low k dielectric effect between word lines. In some embodiments, a bottom bitline structure may be split across multiple layers. In some embodiments, a second tier of vertical cells may be positioned over a first tier of vertical cells.

公开(公告)号：US20230223439A1

公开(公告)日：2023-07-13

申请号：US17715613

申请日：2022-04-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Yang Lai ,  Chun-Yen Peng ,  Tsung-Da Lin ,  Chi On Chui

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/0665 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/66742 ,  H01L21/823412 ,  H01L21/823418

Abstract: An embodiment includes a device including a first high-k gate dielectric on a first channel region of a first semiconductor feature, the first high-k gate dielectric being a crystalline layer with a grain size in a range of 10 Å to 200 Å. The device also includes a first gate electrode on the first high-k gate dielectric. The device also includes a source region and a drain region on opposite sides of the first gate electrode.

公开(公告)号：US11688786B2

公开(公告)日：2023-06-27

申请号：US17189779

申请日：2021-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/4908 ,  H01L21/02603 ,  H01L21/28088 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78696

Abstract: In an embodiment, a device includes: a first channel region; a second channel region; and a gate structure around the first channel region and the second channel region, the gate structure including: a gate dielectric layer; a first p-type work function metal on the gate dielectric layer, the first p-type work function metal including fluorine and aluminum; a second p-type work function metal on the first p-type work function metal, the second p-type work function metal having a lower concentration of fluorine and a lower concentration of aluminum than the first p-type work function metal; and a fill layer on the second p-type work function metal.