公开(公告)号：US11929254B2

公开(公告)日：2024-03-12

申请号：US18072896

申请日：2022-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Ming Lung ,  ChunYao Wang

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8234

CPC classification number: H01L21/0332 ,  H01L21/02164 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31116 ,  H01L21/32139 ,  H01L21/823431 ,  Y10S438/947

Abstract: A method includes depositing a hard mask over a target layer. Depositing the hard mask includes depositing a first hard mask layer having a first density and depositing a second hard mask layer over the first hard mask layer, the second hard mask layer having a second density greater than the first density. The method further includes forming a plurality of mandrels over the hard mask; depositing a spacer layer over and along sidewalls of the plurality of mandrels; patterning the spacer layer to provide a plurality of spacers on the sidewalls of the plurality of mandrels; after patterning the spacer layer, removing the plurality of mandrels; transferring a patterning the plurality of spacers to the hard mask; and patterning the target layer using the hard mask as a mask.

公开(公告)号：US11521856B2

公开(公告)日：2022-12-06

申请号：US17151973

申请日：2021-01-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Ming Lung ,  ChunYao Wang

IPC: H01L21/033 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/302 ,  H01L21/311 ,  H01L21/3213

Abstract: A method includes depositing a hard mask over a target layer. Depositing the hard mask includes depositing a first hard mask layer having a first density and depositing a second hard mask layer over the first hard mask layer, the second hard mask layer having a second density greater than the first density. The method further includes forming a plurality of mandrels over the hard mask; depositing a spacer layer over and along sidewalls of the plurality of mandrels; patterning the spacer layer to provide a plurality of spacers on the sidewalls of the plurality of mandrels; after patterning the spacer layer, removing the plurality of mandrels; transferring a patterning the plurality of spacers to the hard mask; and patterning the target layer using the hard mask as a mask.

公开(公告)号：US20220352348A1

公开(公告)日：2022-11-03

申请号：US17558958

申请日：2021-12-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Ming Lung ,  Che-Hao Chang

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: Embodiments provide a treatment process to a dielectric layer deposited in a source/drain recess. The treatment process alters the etch selectivity of the horizontal portions of the dielectric layer to cause the etch rate of the horizontal portions of the dielectric layer to have a lower etch rate than the vertical portions of the dielectric layer. The vertical portions are removed by a wet etch process to leave a portion of the dielectric layer at a bottom of the source/drain recess.

公开(公告)号：US11728173B2

公开(公告)日：2023-08-15

申请号：US17038499

申请日：2020-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ju Chen ,  Chung-Ting Ko ,  Wan-Chen Hsieh ,  Chun-Ming Lung ,  Tai-Chun Huang ,  Chi On Chui

IPC: H01L21/308 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L21/3085 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02356 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.

公开(公告)号：US20220102152A1

公开(公告)日：2022-03-31

申请号：US17038499

申请日：2020-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ju Chen ,  Chung-Ting Ko ,  Wan-Chen Hsieh ,  Chun-Ming Lung ,  Tai-Chun Huang ,  Chi On Chui

IPC: H01L21/308 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3065 ,  H01L29/66 ,  H01L21/8238

Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.

公开(公告)号：US20240177995A1

公开(公告)日：2024-05-30

申请号：US18434121

申请日：2024-02-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Ming Lung ,  ChunYao Wang

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8234

CPC classification number: H01L21/0332 ,  H01L21/02164 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31116 ,  H01L21/32139 ,  H01L21/823431 ,  Y10S438/947

Abstract: A method includes depositing a hard mask over a target layer. Depositing the hard mask includes depositing a first hard mask layer having a first density and depositing a second hard mask layer over the first hard mask layer, the second hard mask layer having a second density greater than the first density. The method further includes forming a plurality of mandrels over the hard mask; depositing a spacer layer over and along sidewalls of the plurality of mandrels; patterning the spacer layer to provide a plurality of spacers on the sidewalls of the plurality of mandrels; after patterning the spacer layer, removing the plurality of mandrels; transferring a patterning the plurality of spacers to the hard mask; and patterning the target layer using the hard mask as a mask.

公开(公告)号：US20230335406A1

公开(公告)日：2023-10-19

申请号：US18341410

申请日：2023-06-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ju Chen ,  Chung-Ting Ko ,  Wan-Chen Hsieh ,  Chun-Ming Lung ,  Tai-Chun Huang ,  Chi On Chui

IPC: H01L21/308 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3065 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L21/3085 ,  H01L21/823871 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/02603 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/31111 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02356 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L27/092

Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.

公开(公告)号：US20230040843A1

公开(公告)日：2023-02-09

申请号：US17716514

申请日：2022-04-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Ming Lung ,  Che-Hao Chang ,  Zhen-Cheng Wu ,  Chi On Chui

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L21/02 ,  H01L21/265 ,  H01L21/764 ,  H01L21/8238 ,  H01L29/66

Abstract: A method of forming a semiconductor device includes: forming a fin structure protruding above a substrate, where the fin structure includes a fin and a layer stack over the fin, the layer stack comprising alternating layers of a first semiconductor material and a second semiconductor material; forming a first dummy gate structure and a second dummy gate structure over the fin structure; forming an opening in the fin structure between the first dummy gate structure and the second dummy gate structure; converting an upper layer of the fin exposed at a bottom of the opening into a seed layer by performing an implantation process; selectively depositing a dielectric layer over the seed layer at the bottom of the opening; and selectively growing a source/drain material on opposing sidewalls of the second semiconductor material exposed by the opening.

公开(公告)号：US20220102142A1

公开(公告)日：2022-03-31

申请号：US17151973

申请日：2021-01-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Ming Lung ,  ChunYao Wang

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/308 ,  H01L21/8234

Abstract: A method includes depositing a hard mask over a target layer. Depositing the hard mask includes depositing a first hard mask layer having a first density and depositing a second hard mask layer over the first hard mask layer, the second hard mask layer having a second density greater than the first density. The method further includes forming a plurality of mandrels over the hard mask; depositing a spacer layer over and along sidewalls of the plurality of mandrels; patterning the spacer layer to provide a plurality of spacers on the sidewalls of the plurality of mandrels; after patterning the spacer layer, removing the plurality of mandrels; transferring a patterning the plurality of spacers to the hard mask; and patterning the target layer using the hard mask as a mask.