公开(公告)号：US12015066B2

公开(公告)日：2024-06-18

申请号：US17231649

申请日：2021-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yuan Chang ,  Te-Yang Lai ,  Kuei-Lun Lin ,  Xiong-Fei Yu ,  Chi On Chui ,  Tsung-Da Lin ,  Cheng-Hao Hou

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/42364 ,  H01L21/823431 ,  H01L21/823462 ,  H01L27/0924 ,  H01L29/785 ,  H01L2029/7858

Abstract: A method includes providing first and second channel layers in NMOS and PMOS regions respectively of a substrate; depositing a first layer comprising hafnium oxide over the first and second channel layers; forming a first dipole pattern over the second channel layer and not over the first channel layer; driving a first metal from the first dipole pattern into the first layer by annealing; removing the first dipole pattern; depositing a second layer comprising hafnium oxide over the first layer and over the first and second channel layers; forming a second dipole pattern over the second layer and the first channel layer and not over the second channel layer; driving a second metal from the second dipole pattern into the second layer by annealing; removing the second dipole pattern; and depositing a third layer comprising hafnium oxide over the second layer and over the first and the second channel layers.

公开(公告)号：US20240071767A1

公开(公告)日：2024-02-29

申请号：US18150861

申请日：2023-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh-Ju Chen ,  Chi On Chui ,  Tsung-Da Lin ,  Pei Ying Lai ,  Chia-Wei Hsu

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/311 ,  H01L29/40 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L21/28158 ,  H01L21/0206 ,  H01L21/02321 ,  H01L21/02337 ,  H01L21/31122 ,  H01L29/401 ,  H01L29/4908 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/42392

Abstract: A method includes removing a dummy gate stack to form a trench between gate spacers, depositing a gate dielectric extending into the trench, and performing a first treatment process on the gate dielectric. The first treatment process is performed using a fluorine-containing gas. A first drive-in process is then performed to drive fluorine in the fluorine-containing gas into the gate dielectric. The method further includes performing a second treatment process on the gate dielectric, wherein the second treatment process is performed using the fluorine-containing gas, and performing a second drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric. After the second drive-in process, conductive layers are formed to fill the trench.

公开(公告)号：US20230223439A1

公开(公告)日：2023-07-13

申请号：US17715613

申请日：2022-04-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Yang Lai ,  Chun-Yen Peng ,  Tsung-Da Lin ,  Chi On Chui

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/0665 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/66742 ,  H01L21/823412 ,  H01L21/823418

Abstract: An embodiment includes a device including a first high-k gate dielectric on a first channel region of a first semiconductor feature, the first high-k gate dielectric being a crystalline layer with a grain size in a range of 10 Å to 200 Å. The device also includes a first gate electrode on the first high-k gate dielectric. The device also includes a source region and a drain region on opposite sides of the first gate electrode.

公开(公告)号：US20230238241A1

公开(公告)日：2023-07-27

申请号：US17663050

申请日：2022-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyun-Yi Wu ,  Chung-Yi Su ,  Tsung-Da Lin ,  Chi On Chui

IPC: H01L21/28 ,  H01L29/66

CPC classification number: H01L21/28185 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method includes forming a dummy gate stack on a semiconductor region, forming gate spacers on sidewalls of the dummy gate stack, removing the dummy gate stack to form a recess between the gate spacers, and forming a silicon oxide layer on the semiconductor region. The silicon oxide layer extends into the recess. A high-k dielectric layer is deposited over the silicon oxide layer, and a silicon layer is deposited over the high-k dielectric layer. The silicon layer extends into the recess. The high-k dielectric layer and the silicon layer are in-situ deposited in a same vacuum environment. The method further includes performing an annealing process on the silicon layer and the high-k dielectric layer, removing the silicon layer, and forming a gate electrode over the high-k dielectric layer. The gate electrode fills the recess.

公开(公告)号：US20230163129A1

公开(公告)日：2023-05-25

申请号：US17703329

申请日：2022-03-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh-Ju Chen ,  Yi Hsuan Chen ,  Jyun-Yi Wu ,  Wen-Hung Huang ,  Tsung-Da Lin ,  Jian-Hao Chen ,  Cheng-Lung Hung ,  Kuo-Feng Yu

IPC: H01L27/092 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L27/0924 ,  H01L29/1037 ,  H01L29/7851 ,  H01L29/66818 ,  H01L21/823807 ,  H01L21/823821

Abstract: In an embodiment, a device includes: an isolation region on a substrate; a first semiconductor fin protruding above the isolation region; a first gate dielectric on a first channel region of the first semiconductor fin, the first gate dielectric including a first interfacial layer and a first high-k dielectric layer; a second semiconductor fin protruding above the isolation region; and a second gate dielectric on a second channel region of the second semiconductor fin, the second gate dielectric including a second interfacial layer and a second high-k dielectric layer, a first portion of the first interfacial layer on the first channel region having a greater thickness than a second portion of the second interfacial layer on the second channel region, the second channel region having a greater height than the first channel region.

公开(公告)号：US20230178601A1

公开(公告)日：2023-06-08

申请号：US17832342

申请日：2022-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Yang Lai ,  Hsueh-Ju Chen ,  Tsung-Da Lin ,  Chi On Chui

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/0665 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/66742

Abstract: In an embodiment, a semiconductor device includes a first channel region disposed in a first device region over a substrate; a first gate dielectric layer disposed over the first channel region; and a gate electrode disposed over the first gate dielectric layer. The first gate dielectric layer includes a first dipole dopant and a second dipole dopant. The first dipole dopant along a thickness direction of the first gate dielectric layer has a first concentration peak, and the second dipole dopant along the thickness direction of the first gate dielectric layer has a second concentration peak. The second concentration peak is located between the first concentration peak and an upper surface of the first gate dielectric layer. The second concentration peak is offset from the upper surface of the first gate dielectric layer.

公开(公告)号：US20220084889A1

公开(公告)日：2022-03-17

申请号：US17147134

申请日：2021-01-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Yang Lai ,  Hsueh-Ju Chen ,  Tsung-Da Lin ,  Chi On Chui

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A method of forming a semiconductor device includes: forming, in a first device region of the semiconductor device, first nanostructures over a first fin that protrudes above a substrate; forming, in a second device region of the semiconductor device, second nanostructures over a second fin that protrudes above the substrate, where the first and the second nanostructures include a semiconductor material and extend parallel to an upper surface of the substrate; forming a dielectric material around the first and the second nanostructures; forming a first hard mask layer in the first device region around the first nanostructures and in the second device region around the second nanostructures; removing the first hard mask layer from the second device region after forming the first hard mask layer; and after removing the first hard mask layer, increasing a first thickness of the dielectric material around the second nanostructures by performing an oxidization process.

公开(公告)号：US20210399104A1

公开(公告)日：2021-12-23

申请号：US17231649

申请日：2021-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yuan Chang ,  Te-Yang Lai ,  Kuei-Lun Lin ,  Xiong-Fei Yu ,  Chi On Chui ,  Tsung-Da Lin ,  Cheng-Hao Hou

IPC: H01L29/423 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8234

Abstract: A method includes providing first and second channel layers in NMOS and PMOS regions respectively of a substrate; depositing a first layer comprising hafnium oxide over the first and second channel layers; forming a first dipole pattern over the second channel layer and not over the first channel layer; driving a first metal from the first dipole pattern into the first layer by annealing; removing the first dipole pattern; depositing a second layer comprising hafnium oxide over the first layer and over the first and second channel layers; forming a second dipole pattern over the second layer and the first channel layer and not over the second channel layer; driving a second metal from the second dipole pattern into the second layer by annealing; removing the second dipole pattern; and depositing a third layer comprising hafnium oxide over the second layer and over the first and the second channel layers.

公开(公告)号：US20240371997A1

公开(公告)日：2024-11-07

申请号：US18358383

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh-Ju Chen ,  Tsung-Da Lin ,  Chi On Chui

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes forming a source/drain region based on a first portion of a semiconductor region, forming an interfacial layer base on a second portion of the semiconductor region, forming a dipole film on the interfacial layer, depositing a high-k dielectric layer on the dipole film, and depositing a work-function layer on the high-k dielectric layer.

公开(公告)号：US20230369124A1

公开(公告)日：2023-11-16

申请号：US18357449

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Yang Lai ,  Hsueh-Ju Chen ,  Tsung-Da Lin ,  Chi On Chui

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L21/823462 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/823412 ,  H01L29/66742 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/823437 ,  H01L2029/42388

Abstract: A method of forming a semiconductor device includes: forming, in a first device region of the semiconductor device, first nanostructures over a first fin that protrudes above a substrate; forming, in a second device region of the semiconductor device, second nanostructures over a second fin that protrudes above the substrate, where the first and the second nanostructures include a semiconductor material and extend parallel to an upper surface of the substrate; forming a dielectric material around the first and the second nanostructures; forming a first hard mask layer in the first device region around the first nanostructures and in the second device region around the second nanostructures; removing the first hard mask layer from the second device region after forming the first hard mask layer; and after removing the first hard mask layer, increasing a first thickness of the dielectric material around the second nanostructures by performing an oxidization process.