公开(公告)号：US20240347392A1

公开(公告)日：2024-10-17

申请号：US18753130

申请日：2024-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L21/8238 ,  H01L21/285 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L27/0924 ,  H01L29/4966 ,  H01L21/28568

Abstract: A method includes depositing a first conductive layer over a gate dielectric layer; depositing a first work function tuning layer over the first conductive layer; selectively removing the first work function tuning layer from over a first region of the first conductive layer; doping the first work function tuning layer with a dopant; and after doping the first work function tuning layer performing a first treatment process to etch the first region of the first conductive layer and a second region of the first work function tuning layer. The first treatment process etches the first conductive layer at a greater rate than the first work function tuning layer.

公开(公告)号：US12112988B2

公开(公告)日：2024-10-08

申请号：US18361566

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Chi On Chui

IPC: H01L21/82 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/764 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L21/823481 ,  H01L21/28518 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/76229 ,  H01L21/764 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66545

Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. The isolation regions extend into a semiconductor substrate. The method further includes etching a portion of the semiconductor fin to form a trench, filling the trench with a first dielectric material, wherein the first dielectric material has a first bandgap, and performing a recessing process to recess the first dielectric material. A recess is formed between opposing portions of the isolation regions. The recess is filled with a second dielectric material. The first dielectric material and the second dielectric material in combination form an additional isolation region. The second dielectric material has a second bandgap smaller than the first bandgap.

公开(公告)号：US12112942B2

公开(公告)日：2024-10-08

申请号：US17818823

申请日：2022-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Chi On Chui

IPC: H01L21/02 ,  C23C16/455 ,  H01L21/443 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/383

CPC classification number: H01L21/0228 ,  C23C16/45525 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795 ,  H01L21/383 ,  H01L21/443

Abstract: A method includes placing a semiconductor substrate in a deposition chamber, wherein the semiconductor substrate includes a trench, and performing an atomic layer deposition (ALD) process to deposit a dielectric material within the trench, including flowing a first precursor of the dielectric material into the deposition chamber as a gas phase; flowing a second precursor of the dielectric material into the deposition chamber as a gas phase; and controlling the pressure and temperature within the deposition chamber such that the second precursor condenses on surfaces within the trench as a liquid phase of the second precursor, wherein the liquid phase of the second precursor has capillarity.

公开(公告)号：US20240313044A1

公开(公告)日：2024-09-19

申请号：US18184999

申请日：2023-03-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Hung Tsai ,  Cheng-Hao Hou ,  Da-Yuan Lee ,  Chi On Chui

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L28/91 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/7687 ,  H01L23/5223 ,  H01L23/5226

Abstract: A method includes forming a first electrode, performing a first treatment process on a first oxide layer over the first electrode, wherein the first treatment process is performed using a first process gas comprising ammonia, depositing a high-k dielectric layer over the first oxide layer, forming a second electrode over the high-k dielectric layer, forming a first contact plug electrically connecting to the first electrode, and forming a second contact plug electrically connecting to the second electrode.

公开(公告)号：US20240313041A1

公开(公告)日：2024-09-19

申请号：US18184119

申请日：2023-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Hung Tsai ,  Chun-Hsiu Chiang ,  Cheng-Hao Hou ,  Da-Yuan Lee ,  Chi On Chui

IPC: H01L21/768 ,  H01G4/008 ,  H01L23/522

CPC classification number: H01L28/60 ,  H01G4/008 ,  H01L21/76826 ,  H01L21/76832 ,  H01L23/5223 ,  H01L23/5226

Abstract: A method includes forming a first electrode, and depositing a dielectric layer over the first electrode. The dielectric layer has a first dielectric constant and a first thickness. A dielectric capping layer is deposited over the dielectric layer. The dielectric capping layer has a second dielectric constant higher than the first dielectric constant, and a second thickness smaller than the first thickness. The method further includes forming a second electrode over the dielectric capping layer, forming a first contact plug electrically connecting to the first electrode, and forming a second contact plug electrically connecting to the second electrode.

公开(公告)号：US20240304496A1

公开(公告)日：2024-09-12

申请号：US18668960

申请日：2024-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Tai-Chun Huang ,  Jr-Hung Li ,  Tze-Liang Lee ,  Chi On Chui

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545

Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. The isolation regions extend into a semiconductor substrate. A portion of the semiconductor fin is etched to form a trench, which extends lower than bottom surfaces of the isolation regions, and extends into the semiconductor substrate. The method further includes filling the trench with a first dielectric material to form a first fin isolation region, recessing the first fin isolation region to form a first recess, and filling the first recess with a second dielectric material. The first dielectric material and the second dielectric material in combination form a second fin isolation region.

公开(公告)号：US20240282816A1

公开(公告)日：2024-08-22

申请号：US18654298

申请日：2024-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes: a fin protruding above a substrate; source/drain regions over the fin; nanosheets between the source/drain regions; and a gate structure over the fin and between the source/drain regions, the gate structure including: a gate dielectric material around each of the nanosheets; a work function material around the gate dielectric material; a liner material around the work function material, where the liner material has a non-uniform thickness and is thicker at a first location between the nanosheets than at a second location along sidewalls of the nanosheets; and a gate electrode material around at least portions of the liner material.

公开(公告)号：US20240274476A1

公开(公告)日：2024-08-15

申请号：US18644657

申请日：2024-04-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-En Lin ,  Chi On Chui ,  Fang-Yi Liao ,  Chunyao Wang ,  Yung-Cheng Lu

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/762 ,  H01L21/764 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823878 ,  H01L21/28088 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes patterning a trench and depositing a first insulating material along sidewalls and a bottom surface of the trench using a conformal deposition process. Depositing the first insulating material includes forming a first seam between a first portion of the first insulating material on a first sidewall of the trench and a second portion of the first insulating material on a second sidewall of the trench. The method further includes etching the first insulating material below a top of the trench and depositing a second insulating material over the first insulating material and in the trench using a conformal deposition process. Depositing the second insulating material comprises forming a second seam between a first portion of the second insulating material on the first sidewall of the trench and a second portion of the second insulating material on a second sidewall of the trench.

公开(公告)号：US20240258387A1

公开(公告)日：2024-08-01

申请号：US18314446

申请日：2023-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Syuan Siao ,  Meng-Han Chou ,  Chien-Yu Lin ,  Wei-Ting Chang ,  Tien-Shun Chang ,  Chin-I Kuan ,  Su-Hao Liu ,  Chi On Chui

IPC: H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: In an embodiment, a device includes: a first semiconductor nanostructure; a second semiconductor nanostructure adjacent the first semiconductor nanostructure; a first source/drain region on a first sidewall of the first semiconductor nanostructure; a second source/drain region on a second sidewall of the second semiconductor nanostructure, the second source/drain region completely separated from the first source/drain region; and a source/drain contact between the first source/drain region and the second source/drain region.

公开(公告)号：US12015066B2

公开(公告)日：2024-06-18

申请号：US17231649

申请日：2021-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yuan Chang ,  Te-Yang Lai ,  Kuei-Lun Lin ,  Xiong-Fei Yu ,  Chi On Chui ,  Tsung-Da Lin ,  Cheng-Hao Hou

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/42364 ,  H01L21/823431 ,  H01L21/823462 ,  H01L27/0924 ,  H01L29/785 ,  H01L2029/7858

Abstract: A method includes providing first and second channel layers in NMOS and PMOS regions respectively of a substrate; depositing a first layer comprising hafnium oxide over the first and second channel layers; forming a first dipole pattern over the second channel layer and not over the first channel layer; driving a first metal from the first dipole pattern into the first layer by annealing; removing the first dipole pattern; depositing a second layer comprising hafnium oxide over the first layer and over the first and second channel layers; forming a second dipole pattern over the second layer and the first channel layer and not over the second channel layer; driving a second metal from the second dipole pattern into the second layer by annealing; removing the second dipole pattern; and depositing a third layer comprising hafnium oxide over the second layer and over the first and the second channel layers.