公开(公告)号：US11682722B2

公开(公告)日：2023-06-20

申请号：US17529747

申请日：2021-11-18

申请人： MONOLITHIC POWER SYSTEMS, INC.

发明人： Vipindas Pala ,  Sudarsan Uppili

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/423 ,  H01L29/10 ,  H01L29/808 ,  H01L29/06

CPC分类号： H01L29/7803 ,  H01L29/063 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/8083

摘要： The present disclosure describes vertical transistor device and methods of making the same. The vertical transistor device includes substrate layer of first conductivity type, drift layer of first conductivity type formed over substrate layer, body region of second conductivity type extending vertically into drift layer from top surface of drift layer, source region of first conductivity type extending vertically from top surface of drift layer into body region, dielectric region including first and second sections formed over top surface, buried channel region of first conductivity type at least partially sandwiched between body region on first side and first and second sections of dielectric region on second side opposite to first side, gate electrode formed over dielectric region, and drain electrode formed below substrate layer. Dielectric region laterally overlaps with portion of body region. Thickness of first section is uniform and thickness of second section is greater than first section.

公开(公告)号：US20190252498A1

公开(公告)日：2019-08-15

申请号：US16388807

申请日：2019-04-18

申请人： SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.

发明人： Shunichi NAKAMURA ,  Akihiko SUGAI ,  Tetsuto INOUE

IPC分类号： H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L21/04 ,  H01L29/16 ,  H01L29/66 ,  H01L29/739 ,  H01L29/08

CPC分类号： H01L29/1045 ,  H01L21/0465 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7802

摘要： A silicon carbide semiconductor device includes: n type regions formed on a surface of the n− type epitaxial layer; p type body regions formed at positions deeper than the n type regions; p− type channel regions each reaching the p type body region; and n++ type source regions formed toward the p type body region from the front surface side of the epitaxial layer, and the p− type channel regions and the n++ type source regions are formed at a planar position where the n type region remains between the p− type channel region and the n++ type source region, and out of boundary surfaces which are formed between the p− type channel region and the n type regions, the boundary surface on an outer peripheral side is positioned inside an outer peripheral surface 116a of the p type body region as viewed in a plan view.

公开(公告)号：US20190157442A1

公开(公告)日：2019-05-23

申请号：US16233473

申请日：2018-12-27

申请人： Vanguard International Semiconductor Corporation

发明人： Shang-Hui TU ,  Chih-Jen HUANG ,  Jui-Chun CHANG ,  Shin-Cheng LIN ,  Yu-Hao HO ,  Wen-Hsin LIN

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/10

CPC分类号： H01L29/7801 ,  H01L21/2652 ,  H01L21/266 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7816 ,  H01L29/7823 ,  H01L29/7835

摘要： A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.

公开(公告)号：US20190147960A1

公开(公告)日：2019-05-16

申请号：US15918704

申请日：2018-03-12

申请人： Cypress Semiconductor Corporation

发明人： Gary Menezes ,  Krishnaswamy Ramkumar ,  Ali Keshavarzi ,  Venkatraman Prabhakar

IPC分类号： G11C16/10 ,  H01L29/792 ,  H01L29/78 ,  H01L29/51 ,  H01L27/1157 ,  H01L29/08 ,  H01L29/10 ,  H01L29/36 ,  H01L29/167 ,  G11C16/04

CPC分类号： G11C16/107 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/16 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/36 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7883 ,  H01L29/7923

摘要： A memory device that includes a non-volatile memory (NVM) array, divided into a flash memory portion and an electrically erasable programmable read-only memory (EEPROM) portion. The NVM array includes charge-trapping memory cells arranged in rows and columns, in which each memory cell has a memory transistor including an angled lightly doped drain (LDD) implant, and a select transistor including a shared source region with a halo implant. The flash memory portion and the EEPROM portion are disposed within one single semiconductor die. Other embodiments are also disclosed.

公开(公告)号：US20190067471A1

公开(公告)日：2019-02-28

申请号：US16057725

申请日：2018-08-07

申请人： RICHTEK TECHNOLOGY CORPORATION

发明人： Tsung-Yi Huang

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/36 ,  H01L29/66 ,  H01L21/265 ,  H01L21/266

CPC分类号： H01L29/7816 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/761 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/08 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/42368 ,  H01L29/66 ,  H01L29/66681 ,  H01L29/66689

摘要： A high voltage device is formed in a semiconductor substrate, and includes: a first deep well, a lateral lightly doped region, a high voltage well, an isolation region, a body region, a gate, a source, a drain, and a first isolation well. The first deep well and the first isolation well are for electrical isolating the high voltage device from neighboring devices below a top surface of the semiconductor substrate. The lateral lightly doped region is located between the first deep well and the high voltage well in a vertical direction, and the lateral lightly doped region contacts the first deep well and the high voltage well. The lateral lightly doped region is for reducing an inner capacitance of the high voltage device when the high voltage device operates, to improve transient response.

公开(公告)号：US20180269279A1

公开(公告)日：2018-09-20

申请号：US15986942

申请日：2018-05-23

申请人： Infineon Technologies AG

发明人： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum ,  Michaela Braun ,  Christian Eckl

IPC分类号： H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H03F3/193 ,  H01L21/768 ,  H03F1/02

CPC分类号： H01L29/063 ,  H01L21/26513 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/4175 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7823 ,  H01L29/7835 ,  H03F1/0288 ,  H03F3/193 ,  H03F2200/451

摘要： In an embodiment, a semiconductor device includes a semiconductor substrate having a bulk resistivity ρ≥100 Ohm.cm, a front surface and a rear surface. An LDMOS transistor is arranged in the semiconductor substrate. A RESURF structure including a doped buried layer is arranged in the semiconductor substrate. The LDMOS transistor includes a body contact region doped with a first conductivity type, and a source region disposed in the body contact region and doped with a second conductivity type opposite the first conductivity type. The source region includes a first well and a second well of the same second conductivity type. The first well is more highly doped than the second well. The first well extends from inside the body contact region to outside of a lateral extent of the body contact region in a direction towards a source side of a gate of the LDMOS transistor.

公开(公告)号：US20180254339A1

公开(公告)日：2018-09-06

申请号：US15896490

申请日：2018-02-14

申请人： Panasonic Intellectual Property Management Co., Ltd.

发明人： TSUTOMU KIYOSAWA

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/417 ,  H01L29/08 ,  H01L29/423

CPC分类号： H01L29/7805 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/7828 ,  H01L2924/13091

摘要： A semiconductor epitaxial wafer includes a semiconductor wafer, and a semiconductor layer of a first conductivity type disposed on a main surface of the semiconductor wafer. The semiconductor epitaxial wafer includes a plurality of device regions. The plurality of device regions each include a body region of a second conductivity type in contact with the semiconductor layer, a source region of the first conductivity type in contact with the body region, and a channel layer that is constituted by a semiconductor, and that is disposed on the semiconductor layer so as to be in contact with at least a part of the body region. In a plane parallel to the main surface of the semiconductor wafer, a thickness distribution in the channel layer and a concentration distribution of the first conductivity type impurity in the channel layer are negatively correlated to each other.

公开(公告)号：US20180212048A1

公开(公告)日：2018-07-26

申请号：US15659539

申请日：2017-07-25

申请人： Vishay-Siliconix

发明人： Wenjie Zhang ,  Madhur Bobde ,  Qufei Chen ,  Kyle Terrill

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/40 ,  H01L29/10 ,  H01L29/06 ,  H01L21/265

CPC分类号： H01L29/781 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/0626 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66492 ,  H01L29/66659 ,  H01L29/66696 ,  H01L29/66712 ,  H01L29/7835

摘要： A laterally diffused metal oxide semiconductor (LDMOS) transistor structure with improved unclamped inductive switching immunity. The LDMOS includes a substrate and an adjacent epitaxial layer both of a first conductivity type. A gate structure is above the epitaxial layer. A drain region and a source region, both of a second conductivity type, are within the epitaxial layer. A channel is formed between the source and drain region and arranged below the gate structure. A body structure of the first conductivity type is at least partially formed under the gate structure and extends laterally under the source region, wherein the epitaxial layer is less doped than the body structure. A conductive trench-like feed-through element passes through the epitaxial layer and contacts the substrate and the source region. The LDMOS includes a tub region of the first conductivity type formed under the source region, and adjacent laterally to and in contact with said body structure and said trench-like feed-through element.

公开(公告)号：US20180211879A1

公开(公告)日：2018-07-26

申请号：US15926248

申请日：2018-03-20

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kangguo Cheng ,  Juntao Li ,  Chun-Chen Yeh

IPC分类号： H01L21/8234 ,  H01L29/78 ,  H01L21/265 ,  H01L21/306 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L21/762 ,  H01L21/324 ,  H01L21/308 ,  H01L21/84

CPC分类号： H01L21/823412 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/324 ,  H01L21/76205 ,  H01L21/76224 ,  H01L21/76237 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1054 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

摘要： A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the dielectric fill into the trenches to form shallow trench isolation regions. The fins are etched above the shallow trench isolation regions to form a staircase fin structure with narrow top portions of the fins. Gate structures are formed over the top portions of the fins. Raised source ad drain regions are epitaxially grown on opposite sides of the gate structure. A pre-morphization implant is performed to generate defects in the substrate to couple strain into the top portions of the fins.

公开(公告)号：US20180197991A1

公开(公告)日：2018-07-12

申请号：US15915105

申请日：2018-03-08

申请人： Magnachip Semiconductor, Ltd.

发明人： Young Bae KIM ,  Kwang Il KIM

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/808 ,  H01L29/66

CPC分类号： H01L29/7832 ,  H01L27/085 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/1045 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66901 ,  H01L29/7835 ,  H01L29/808

摘要： The present examples relate to a junction field effect transistor (JFET) that shares a drain with a high voltage field effect transistor. The present examples are able to control a pinch-off feature of the junction transistor while also maintaining electric features of the high voltage transistor by forming a groove on a lower part of a first conductivity type deep-well region located on a channel region of the junction transistor in a channel width direction.