公开(公告)号：US20190147960A1

公开(公告)日：2019-05-16

申请号：US15918704

申请日：2018-03-12

Applicant: Cypress Semiconductor Corporation

Inventor： Gary Menezes ,  Krishnaswamy Ramkumar ,  Ali Keshavarzi ,  Venkatraman Prabhakar

IPC: G11C16/10 ,  H01L29/792 ,  H01L29/78 ,  H01L29/51 ,  H01L27/1157 ,  H01L29/08 ,  H01L29/10 ,  H01L29/36 ,  H01L29/167 ,  G11C16/04

CPC classification number: G11C16/107 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/16 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/36 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7883 ,  H01L29/7923

Abstract: A memory device that includes a non-volatile memory (NVM) array, divided into a flash memory portion and an electrically erasable programmable read-only memory (EEPROM) portion. The NVM array includes charge-trapping memory cells arranged in rows and columns, in which each memory cell has a memory transistor including an angled lightly doped drain (LDD) implant, and a select transistor including a shared source region with a halo implant. The flash memory portion and the EEPROM portion are disposed within one single semiconductor die. Other embodiments are also disclosed.

公开(公告)号：US20190088487A1

公开(公告)日：2019-03-21

申请号：US16058310

申请日：2018-08-08

Applicant: Cypress Semiconductor Corporation

Inventor： Krishnaswamy Ramkumar ,  Igor Kouznetsov ,  Venkatraman Prabhakar ,  Ali Keshavarzi

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H01L21/02 ,  H01L27/11573 ,  H01L27/11568

CPC classification number: H01L29/40117 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02301 ,  H01L21/02323 ,  H01L21/02337 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66833 ,  H01L29/792

Abstract: A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate oxide structure. The memory device may include a non-volatile memory (NVM) transistor that has a charge-trapping layer and a blocking dielectric, a first field-effect transistor (FET) including a first gate oxide of a first thickness, a second FET including a second gate oxide of a second thickness, a third FET including a third gate oxide of a third thickness, in which the first thickness is greater than the second thickness and the second thickness is greater than the third thickness.

公开(公告)号：US09624094B1

公开(公告)日：2017-04-18

申请号：US15088557

申请日：2016-04-01

Applicant: Cypress Semiconductor Corporation

Inventor： Shan Sun ,  Ali Keshavarzi ,  Thomas Davenport ,  Thurman John Rodgers

IPC: B81B7/00

CPC classification number: B81B7/007 ,  B81B7/0025 ,  B81B2201/0292 ,  B81B2201/032 ,  B81B2207/07 ,  B81B2207/097 ,  H01L28/57 ,  H01L2224/16225 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A microelectronic system including hydrogen barriers and copper pillars for wafer level packaging and method of fabricating the same are provided. Generally, the method includes: forming an insulating hydrogen barrier over a surface of a first chip; exposing at least a portion of an electrical contact electrically coupled to a component in the first chip by removing a portion of the insulating hydrogen barrier, the component including a material susceptible to degradation by hydrogen; forming a conducting hydrogen barrier over at least the exposed portion of the electrical contact; and forming a copper pillar over the conducting hydrogen barrier. In one embodiment, the material susceptible to degradation is lead zirconate titanate (PZT) and the microelectronic systems device is a ferroelectric random access memory including a ferroelectric capacitor with a PZT ferroelectric layer. Other embodiments are also disclosed.

公开(公告)号：US10062573B1

公开(公告)日：2018-08-28

申请号：US15683274

申请日：2017-08-22

Applicant: Cypress Semiconductor Corporation

Inventor： Krishnaswamy Ramkumar ,  Igor Kouznetsov ,  Venkatraman Prabhakar ,  Ali Keshavarzi

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11568 ,  H01L27/11573 ,  H01L21/02

CPC classification number: H01L29/40117 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02301 ,  H01L21/02323 ,  H01L21/02337 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66833 ,  H01L29/792

Abstract: A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate oxide structure. The memory device may include a non-volatile memory (NVM) transistor that has a charge-trapping layer and a blocking dielectric, a first field-effect transistor (FET) including a first gate oxide of a first thickness, a second FET including a second gate oxide of a second thickness, a third FET including a third gate oxide of a third thickness, in which the first thickness is greater than the second thickness and the second thickness is greater than the third thickness.